Methods and circuits for controlling multicycle path in serializer interface
Various example embodiments herein provide methods, circuits, and systems, for controlling a multicycle path in a serializer interface. The method includes determining a desired delay window of a multicycle data path in a serializer interface by sampling at least one step response from serializer delay replica circuitry at an edge of a first clock signal and a gating signal, in response to synchronizing a second clock signal with a negative edge of the first clock signal, configuring a polarity of a latch in a subsequent serializer of a serializer chain based on the determined desired delay window, and controlling the multicycle data path in the serializer interface based on the configured polarity of the latch in the subsequent serializer of the serializer chain.
1 . A method for controlling a multicycle data path in a serializer interface, comprising:
determining a desired delay window of a multicycle data path in a serializer interface by sampling at least one step response from serializer delay replica circuitry at an edge of a first clock signal and a gating signal, in response to synchronizing a second clock signal with a negative edge of the first clock signal;
configuring a polarity of a latch in a subsequent serializer of a serializer chain based on the determined desired delay window; and
controlling the multicycle data path in the serializer interface based on the configured polarity of the latch in the subsequent serializer of the serializer chain.
2 . The method as claimed in claim 1 , wherein
the first clock signal is a C8 clock signal, and
the second clock signal is a C16 clock signal.
3 . The method as claimed in claim 1 , wherein the configuring the polarity of the latch in the subsequent serializer of the serializer chain further includes:
configuring the polarity to be a positive polarity in response to a data delay of the sampled at least one step response being less than 0.5 unit interval (UI).
4 . The method as claimed in claim 1 , wherein the configuring the polarity of the latch in the subsequent serializer of the serializer chain further includes:
configuring the polarity to be a negative polarity in response to a data delay of the sampled at least one step response being greater than 0.5 UI.
5 . The method as claimed in claim 1 , wherein the determining the desired delay window includes using a plurality of samples.
6 . The method as claimed in claim 1 , further comprises:
determining whether a total path delay is observed to be within 0.5 clock period to 1.5 clock period; and
replacing a positive edge triggered flop with a negative edge triggered flop based on results of the determining.
7 . The method as claimed in claim 1 , wherein the serializer delay replica circuitry comprises:
replica last stage circuitry coupled to a plurality of complementary metal-oxide semiconductor (CMOS) buffers;
each CMOS buffer from the plurality of CMOS buffers is coupled to each D-flip-flop from a plurality of D-flip-flops, respectively;
each of the D-flip-flops configured to provide an output signal to voting mechanism circuitry; and
the voting mechanism circuitry is configured to provide a voting signal to a C8TX replica circuit.
8 . A circuit for controlling a multicycle data path in a serializer interface, comprising:
serializer delay replica circuitry configured to:
determine a desired delay window of a multicycle data path in a serializer interface by sampling at least one step response at the serializer delay replica circuitry at an edge of a first clock signal and a gating signal, in response to synchronizing a second clock signal with a negative edge of the first clock signal;
configure a polarity of a latch in a subsequent serializer of a serializer chain based on the determined desired delay window; and
control the multicycle data path in the serializer interface based on the configured polarity of the latch in the subsequent serializer of the serializer chain.
9 . The circuit as claimed in claim 8 , wherein
the first clock signal is a C8 clock signal, and
the second clock signal is a C16 clock signal.
10 . The circuit as claimed in claim 8 , wherein the serializer delay replica circuitry comprises:
replica last stage circuitry coupled to a plurality of complementary metal-oxide semiconductor (CMOS) buffers,
the plurality of CMOS buffers are coupled to a plurality of D-flip-flops, and
the plurality of D-flip-flops is coupled to voting mechanism circuitry.
11 . The circuit as claimed in claim 10 , wherein
each CMOS buffer from the plurality of CMOS buffers is coupled to each D-flip-flop from the plurality of D-flip-flops, respectively,
each D-flip-flop is configured to provide an output signal to the voting mechanism circuitry, and
the voting mechanism circuitry is configured to output a voting signal to a C8TX replica circuit.
12 . A circuit for controlling a multicycle data path in a serializer interface, comprising:
serializer delay replica circuitry configured to:
detect whether a delay in a multicycle data path in a serializer interface is less than a desired value; and
control a direction of a clock of a latch for the multicycle path in the serializer interface based on the detected delay.
13 . The circuit as claimed in claim 12 , wherein the desired value is 0.5 unit interval (UI).
14 . The circuit as claimed in claim 12 , further comprising:
replica last stage circuitry coupled to a plurality of complementary metal-oxide semiconductor (CMOS) buffers,
each CMOS buffer from the plurality of CMOS buffers is coupled to each D-flip-flop from a plurality of D-flip-flops, respectively,
each D-flip-flop is configured to provide an output to voting mechanism circuitry, and
the voting mechanism circuitry is configured to provide a voting output signal to a C8TX replica circuit.