Circuit with two digital-to-analog converters and method of operating such the circuit
A circuit 100 is described comprising (i) a first digital-to-analog converter 110 , (ii) a second digital-to-analog converter 111 , (iii) a plurality of unit elements 120 , and (iv) switching circuitry 130 . The switching circuitry 130 is adapted so that in a first switching state 231 , a set of unit elements 221 of the plurality of unit elements 120 forms part of the first digital-to-analog converter 110 , and in a second switching state 232 , the set of unit elements 221 forms part of the second digital-to-analog converter 111 . Furthermore, a corresponding method of operating a circuit 100 is described.
1. A pipeline converter circuit comprising
a first stage that includes a first input configured to receive a first stage input signal, a first output configured to produce a first stage output signal, and a first digital-to-analog converter coupled between the first input and the first output, wherein the first digital-to-analog converter is configured to receive a first digital signal derived from the first stage input signal, and to produce a first analog signal from which the first stage output signal is derived;
a second stage that includes a second input coupled to the first output and configured to receive the first stage output signal, a second output configured to produce a second stage output signal, and a second digital-to-analog converter coupled between the second input and the second output, wherein the second digital-to-analog converter is configured to receive a second digital signal derived from the first stage output signal, and to produce a second analog signal from which the second stage output signal is derived;
a plurality of unit elements; and
switching circuitry coupled to the first and second stages and to the plurality of unit elements, wherein the switching circuitry is adapted so that, in a first switching state, a set of unit elements of the plurality of unit elements forms part of the first digital-to-analog converter, and in a second switching state, the set of unit elements forms part of the second digital-to-analog converter, wherein the set of unit elements includes fewer than all of the unit elements in the plurality of unit elements.
2. The circuit of claim 1 , wherein each of the unit elements of the plurality of unit elements comprises at least one electric component.
3. The circuit of claim 2 , wherein the at least one electric component is selected from at least one of a group of electric components consisting of a current source, a resistor, and a capacitor.
4. The circuit of claim 1 , wherein a size of the set of unit elements is indicative of a number of bits processed by the first digital-to-analog converter.
5. The circuit of claim 1 , further comprising
at least one further digital-to-analog converter, wherein the switching circuitry is adapted so that, for each further digital-to-analog converter, the set of unit elements forms part of the further digital-to-analog converter in a respective further switching state of the switching circuitry.
6. The circuit of claim 1 , wherein the set of unit elements forming part of the first digital-to-analog converter in the first switching state is selected based on an input value of an input signal received by the first digital-to-analog converter.
7. The circuit of claim 1 , wherein the set of unit elements forming part of the first digital-to-analog converter in the first switching state is selected based on a previous set of unit elements that include different unit elements from the first set of unit elements, which formed part of the first digital-to analog converter, when a previous input value of a previous input signal was processed by the first digital-to analog converter.
8. The circuit of claim 1 , wherein the switching circuitry is adapted so that, in the first switching state, a further set of unit elements forms part of the second digital-to-analog converter, wherein the set of unit elements includes different unit elements from the further set of unit elements, and the further set of unit elements are selected such that a first average gain error of the first digital-to-analog converter equals a second average gain error of the second digital-to-analog converter.
9. The circuit of claim 1 , wherein subsequent sets of unit elements are selected that are different from the set of unit elements to form part of the first digital-to-analog converter when subsequent input signals having respective subsequent input values are received by the first digital-to-analog converter so that respective subsequent deviations from an average error compensate each other.
10. The circuit of claim 1 , wherein subsequent sets of unit elements are selected that are different from the set of unit elements to form part of the first digital-to-analog converter when subsequent input signals having respective subsequent input values are received by the first digital-to-analog converter to noise shape a gain error of the first digital-to-analog converter.
11. The circuit of claim 1 , wherein subsequent further sets of unit elements are selected randomly that are different from the set of unit elements to form part of the second digital-to-analog converter when subsequent further input signals having respective subsequent further input values are received by the second digital-to-analog converter.
12. The circuit of claim 1 , wherein the switching circuitry is configured to electrically connect the set of unit elements to the first digital-to-analog converter in a predetermined order, wherein the order is changed for subsequent input signals.
13. The circuit of claim 1 , further comprising a control device configured to operate the switching circuitry.
14. A method of operating a pipeline converter circuit, which comprises a plurality of stages each including a digital-to-analog converter, and a plurality of unit elements, wherein the method comprises the steps of:
setting, at a first time, switching circuitry of the pipeline converter circuit to a first switching state so that a set of unit elements of the plurality of unit elements forms part of a first digital-to-analog converter of a first stage of the plurality of stages, wherein the set of unit elements includes fewer than all of the unit elements in the plurality of unit elements; and
setting, at a different time, the switching circuitry to a second switching state so that the set of unit elements forms part of a second digital-to-analog converter of a second stage of the plurality of stages.
15. The method of claim 14 , wherein each of the unit elements of the plurality of unit elements comprises at least one electric component.
16. The method of claim 14 , wherein a size of the set of unit elements is indicative of a number of bits processed by the first digital-to-analog converter.
17. The method of claim 14 , wherein the set of unit elements forming part of the first digital-to-analog converter in the first switching state is selected based on an input value of an input signal received by the first digital-to-analog converter.
18. The method of claim 14 , wherein the set of unit elements forming part of the first digital-to-analog converter in the first switching state is selected based on a previous set of unit elements, which formed part of the first digital-to analog converter, when a previous input value of a previous input signal was processed by the first digital-to analog converter.
19. The method of claim 14 , wherein the switching circuitry is adapted so that, in the first switching state, a further set of unit elements that is different from the set of unit elements forms part of the second digital-to-analog converter, wherein the set of unit elements and the further set of unit elements are selected such that a first average gain error of the first digital-to-analog converter equals a second average gain error of the second digital-to-analog converter.
20. The method of claim 14 , wherein subsequent sets of unit elements are selected that are different from the set of unit elements to form part of the first digital-to-analog converter when subsequent input signals having respective subsequent input values are received by the first digital-to-analog converter so that respective subsequent deviations from an average error compensate each other.