IP Library › Granted Patent US 12,437,704

Granted Patent B2

US 12,437,704 · App. 18/358,327 · Granted Oct 7, 2025

Display panel, method for driving the same, and display device

Inventor: Rui Li (Wuhan, CN)

Assignee: WuHan TianMa Micro-electronics Co., Ltd.

G09G3/32 G09G2300/0452 G09G2300/0842 G09G2300/0861 G09G2310/08 G09G2320/0242

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Quick Facts

Patent No.: US 12,437,704
App. No.: 18/358,327
Granted: Oct 7, 2025
Kind: B2

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Abstract

A display panel including sub-pixels each including a pixel circuit and a light-emitting element. The pixel circuit includes a plurality of anode reset circuits. The sub-pixels include a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Anode reset circuits in the red sub-pixel and the blue sub-pixel are configured to respectively reset anodes of the light-emitting elements in the red sub-pixel and the blue sub-pixel by using a first anode reset voltage. The anode reset circuit of the green sub-pixel is configured to reset an anode of the light-emitting element of the green sub-pixel by using a second anode reset voltage greater than the first anode reset voltage.

Claims (103)

1. A display panel, comprising:

a plurality of sub-pixels each comprising a pixel circuit and a light-emitting element,

wherein the pixel circuit comprises an anode reset module;

wherein the plurality of sub-pixels comprises a red sub-pixel, a green sub-pixel, and a blue sub-pixel, wherein the anode reset module of the red sub-pixel is configured to reset an anode of the light-emitting element of the red sub-pixel by using a first anode reset voltage, wherein the anode reset module of the blue sub-pixel is configured to reset an anode of the light-emitting element of the blue sub-pixel by using the first anode reset voltage, wherein the anode reset module of the green sub-pixel is configured to reset an anode of the light-emitting element of the green sub-pixel by using a second anode reset voltage; and

wherein the pixel circuit further comprises a driving transistor and a plurality of gate reset circuits, wherein the plurality of gate reset circuits correspond to each pixel of the plurality of sub-pixels, wherein gate reset circuits of the red sub-pixel, the green sub-pixel, and the blue sub-pixel are configured to respectively reset gates of the drive transistors of the red sub-pixel, the green sub-pixel, and the blue sub-pixel by using a same gate reset voltage.

2. The display panel according to claim 1 , wherein the gate reset voltage is equal to the first anode reset voltage or the second anode reset voltage.

3. The display panel according to claim 1 , wherein the gate reset voltage is not equal to either the first anode reset voltage or the second anode reset voltage.

4. The display panel according to claim 3 , wherein the gate reset voltage is smaller than the first anode reset voltage.

5. The display panel according to claim 1 , further comprising:

pixel columns arranged along a first direction wherein the pixel columns comprise two or more sub-pixels of the plurality of sub-pixels arranged along a second direction, wherein the first direction crosses the second direction;

first anode reset lines extending along the second direction and electrically connected to the anode reset modules of the red sub-pixel and the blue sub-pixel of a pixel column of the pixel columns; and

second anode reset lines extending along the second direction and electrically connected to the anode reset module of the green sub-pixel of a pixel column of the pixel columns.

6. The display panel according to claim 5 , wherein the pixel columns comprise first pixel columns and second pixel columns that are alternately arranged along the first direction, wherein at least one of the first pixel columns comprises red sub-pixels and blue sub-pixels that are alternately arranged along the second direction, and wherein at least one of the second pixel column comprises green sub-pixels arranged along the second direction, and

wherein at least one of the first anode reset lines corresponds to one first pixel column of the first pixel columns and is electrically connected to the anode reset modules of the one first pixel column, and at least one of the second anode reset line corresponds to one second pixel column of the second pixel columns and is electrically connected to the anode reset modules of the one second pixel column.

7. The display panel according to claim 5 , further comprising:

pixel rows arranged along the second direction and comprising two or more sub-pixels of the plurality of sub-pixels arranged along the first direction; and

gate reset lines extending along the first direction, wherein one gate reset line of the gate reset lines is electrically connected to the gate reset circuits of the sub-pixels in one pixel row of the pixel rows.

8. The display panel according to claim 7 , wherein the gate reset voltage is equal to the first anode reset voltage, and wherein the gate reset lines are electrically connected to the first anode reset lines, respectively, or

wherein the gate reset voltage is equal to the second anode reset voltage, and wherein the gate reset lines are electrically connected to the second anode reset lines, respectively.

9. The display panel according to claim 5 , further comprising:

gate reset lines extending along the second direction and electrically connected to the gate reset circuits of the sub-pixels in the pixel columns, respectively.

10. The display panel according to claim 9 , wherein the gate reset voltage is equal to the first anode reset voltage, and the first anode reset lines are electrically connected to the gate reset circuits in the pixel column that is connected to the first anode reset line, respectively, or

wherein the gate reset voltage is equal to the second anode reset voltage, and the second anode reset lines are electrically connected to the gate reset circuits in the pixel column that is connected to the first anode reset line, respectively.

11. The display panel according to claim 9 , wherein one gate reset line of the gate reset lines is electrically connected to the gate reset circuits in two adjacent pixel columns of the pixel columns.

12. The display panel according to claim 1 , further comprising:

pixel rows arranged along a second direction and comprising two or more sub-pixels of the plurality of sub-pixels arranged along a first direction, wherein the second direction crosses the first direction;

first anode reset lines extending along the first direction and electrically connected to anode reset modules in first sub-pixels in a pixel row of the pixel rows, respectively;

second anode reset lines extending along the first direction and electrically connected to anode reset modules in second sub-pixels in a pixel row of the pixel rows, respectively; and

gate reset lines extending along the first direction and electrically connected to the gate reset circuits in the sub-pixels in a pixel row of the pixel rows, respectively.

13. The display panel according to claim 12 , further comprising:

first auxiliary anode reset lines extending along the second direction and electrically connected to the first anode reset lines, respectively; and

second auxiliary anode reset lines extending along the second direction and electrically connected to the second anode reset lines, respectively.

14. The display panel according to claim 13 , further comprising:

pixel columns arranged along the first direction and comprising two or more sub-pixels of the plurality of sub-pixels arranged along the second direction,

wherein the first auxiliary anode reset lines are arranged alternately with the second auxiliary anode reset lines, and a first auxiliary anode reset line of the first auxiliary anode reset lines is spaced apart from a second auxiliary anode reset line of the second auxiliary anode reset lines that is adjacent to the first auxiliary anode reset line by two or more of the pixel columns.

15. The display panel according to claim 5 , wherein the pixel circuit further comprises a data writing circuit electrically connected to a data line and a first electrode of the driving transistor,

wherein the first anode reset line and the data line are arranged in different layers of the display panel, and along a direction perpendicular to a plane of the display panel, the first anode reset line at least partially overlaps the data line, or

wherein the second anode reset line and the data line are arranged in different layers of the display panel, and along the direction perpendicular to the plane of the display panel, the second anode reset line at least partially overlaps the data line.

16. The display panel according to claim 5 , wherein the pixel circuit further comprises a first light-emitting control circuit electrically connected to a power supply line and a first electrode of the driving transistor,

wherein the first anode reset line and the power supply line are arranged in different layers of the display panel, and, along a direction perpendicular to a plane of the display panel, the first anode reset line at least partially overlaps the power supply line, or

wherein the second anode reset line and the power supply line are arranged in different layers of the display panel, and, along the direction perpendicular to the plane of the display panel, the second anode reset line at least partially overlaps the power supply line.

17. The display panel according to claim 1 , wherein a turn-on voltage of the light-emitting element in the green sub-pixel is smaller than turn-on voltages of the light-emitting elements in the red sub-pixel and the blue sub-pixel.

18. A method for driving a display panel, wherein the display panel comprises a plurality of sub-pixels each comprising a pixel circuit and a light-emitting element, wherein the pixel circuit comprises an anode reset module, wherein the plurality of sub-pixels comprises a red sub-pixel, a green sub-pixel, and a blue sub-pixel, the anode reset module of the red sub-pixel is configured to reset an anode of the light-emitting element of the red sub-pixel by using a first anode reset voltage, the anode reset module of the blue sub-pixel is configured to reset an anode of the light-emitting element of the blue sub-pixel by using the first anode reset voltage, and the anode reset module of the green sub-pixel is configured to reset an anode of the light-emitting element of the green sub-pixel by using a second anode reset voltage, and wherein the pixel circuit further comprises a driving transistor and a plurality of gate reset circuits, wherein the plurality of gate reset circuits correspond to each pixel of the plurality of sub-pixels, wherein gate reset circuits of the first-color sub-pixel, the second-color sub-pixel, and the third-color sub-pixel are configured to respectively reset gates of the drive transistors of the first-color sub-pixel, the second-color sub-pixel, and the third-color sub-pixel by using a same gate reset voltage,

the method comprising:

controlling the anode reset modules in the red sub-pixel and the blue sub-pixel to reset the anodes of the light-emitting elements in the red sub-pixel and the blue sub-pixel by using a first anode reset voltage; and

controlling the anode reset module of the green sub-pixel to reset the anode of the light-emitting element of the green sub-pixel by using the second anode reset voltage greater than the first anode reset voltage.

19. A display device comprising a display panel, wherein the display panel comprises:

a plurality of sub-pixels each comprising a pixel circuit and a light-emitting element,

wherein the pixel circuit comprises an anode reset module;

wherein the plurality of sub-pixels comprises a red sub-pixel, a green sub-pixel, and a blue sub-pixel, an anode reset module of the red sub-pixel is configured to reset an anode of the light-emitting element of the red sub-pixel by using a first anode reset voltage, an anode reset module of the blue sub-pixel is configured to reset an anode of the light-emitting element of the blue sub-pixel by using the first anode reset voltage, and an anode reset module of the green sub-pixel is configured to reset an anode of the light-emitting element of the green sub-pixel by using a second anode reset voltage; and

wherein the pixel circuit further comprises a driving transistor and a plurality of gate reset circuits, wherein the plurality of gate reset circuits correspond to each pixel of the plurality of sub-pixels, wherein gate reset circuits of the first-color sub-pixel, the second-color sub-pixel, and the third-color sub-pixel are configured to respectively reset gates of the drive transistors of the first-color sub-pixel, the second-color sub-pixel, and the third-color sub-pixel by using a same gate reset voltage.

20. A display panel, comprising:

a plurality of sub-pixels each comprising a pixel circuit and a light-emitting element,

wherein the pixel circuit comprises an anode reset module;

wherein the plurality of sub-pixels comprises a first-color sub-pixel, a second-color sub-pixel, and a third-color sub-pixel, wherein the first anode reset module is configured to reset an anode of the light-emitting element of the first-color sub-pixel by using a first anode reset voltage, wherein the third anode reset module is configured to reset an anode of the light-emitting element of the third-color sub-pixel by using the first anode reset voltage, wherein the second anode reset module is configured to reset an anode of the light-emitting element of the second-color sub-pixel by using a second anode reset voltage; and

the pixel circuit further comprises a driving transistor and a plurality of gate reset circuits, wherein the plurality of gate reset circuits correspond to each pixel of the plurality of sub-pixels, wherein gate reset circuits of the first-color sub-pixel, the second-color sub-pixel, and the third-color sub-pixel are configured to respectively reset gates of the drive transistors of the first-color sub-pixel, the second-color sub-pixel, and the third-color sub-pixel by using a same gate reset voltage.

21. The display panel according to claim 20 , wherein the gate reset voltage is equal to the first anode reset voltage or the second anode reset voltage.

22. The display panel according to claim 20 , wherein the gate reset voltage is not equal to either the first anode reset voltage or the second anode reset voltage.

23. The display panel according to claim 22 , wherein the gate reset voltage is smaller than the first anode reset voltage.

24. The display panel according to claim 20 , further comprising:

first anode reset lines extending along the second direction and electrically connected to the anode reset modules of the first-color sub-pixel and the third-color sub-pixel of a pixel column of the pixel columns; and

second anode reset lines extending along the second direction and electrically connected to the anode reset module of the second-color sub-pixel of a pixel column of the pixel columns.

25. The display panel according to claim 24 , wherein the pixel columns comprise first pixel columns and second pixel columns that are alternately arranged along the first direction, wherein at least one of the first pixel columns comprises first-color sub-pixels and third-color sub-pixels that are alternately arranged along the second direction, and wherein at least one of the second pixel column comprises second-color sub-pixels arranged along the second direction, and

26. The display panel according to claim 24 , further comprising:

pixel rows arranged along the second direction and comprising two or more sub-pixels of the plurality of sub-pixels arranged along the first direction; and

27. The display panel according to claim 26 , wherein the gate reset voltage is equal to the first anode reset voltage, and wherein the gate reset lines are electrically connected to the first anode reset lines, respectively, or

wherein the gate reset voltage is equal to the second anode reset voltage, and wherein the gate reset lines are electrically connected to the second anode reset lines, respectively.

28. The display panel according to claim 24 , further comprising:

gate reset lines extending along the second direction and electrically connected to the gate reset circuits of the sub-pixels in the pixel columns, respectively.

29. The display panel according to claim 28 , wherein the gate reset voltage is equal to the first anode reset voltage, and the first anode reset lines are electrically connected to the gate reset circuits in the pixel column that is connected to the first anode reset line, respectively, or

30. The display panel according to claim 28 , wherein one gate reset line of the gate reset lines is electrically connected to the gate reset circuits in two adjacent pixel columns of the pixel columns.

31. The display panel according to claim 20 , further comprising:

first anode reset lines extending along the first direction and electrically connected to anode reset modules in first sub-pixels in a pixel row of the pixel rows, respectively;

second anode reset lines extending along the first direction and electrically connected to anode reset modules in second sub-pixels in a pixel row of the pixel rows, respectively; and

gate reset lines extending along the first direction and electrically connected to the gate reset circuits in the sub-pixels in a pixel row of the pixel rows, respectively.

32. The display panel according to claim 31 , further comprising:

first auxiliary anode reset lines extending along the second direction and electrically connected to the first anode reset lines, respectively; and

second auxiliary anode reset lines extending along the second direction and electrically connected to the second anode reset lines, respectively.

33. The display panel according to claim 32 , further comprising:

pixel columns arranged along the first direction and comprising two or more sub-pixels of the plurality of sub-pixels arranged along the second direction,

34. The display panel according to claim 24 , wherein the pixel circuit further comprises a data writing circuit electrically connected to a data line and a first electrode of the driving transistor,

35. The display panel according to claim 24 , wherein the pixel circuit further comprises a first light-emitting control circuit electrically connected to a power supply line and a first electrode of the driving transistor,

36. The display panel according to claim 20 , wherein a turn-on voltage of the light-emitting element in the second-color sub-pixel is smaller than turn-on voltages of the light-emitting elements in the first-color sub-pixel and the third-color sub-pixel.

37. The display panel according to claim 20 , further comprising:

first anode reset lines configured to provide the first anode reset voltage;

second anode reset lines configured to provide the second anode reset voltage, and

gate reset line configured to provide the gate reset voltage.

38. The display panel according to claim 37 , wherein

at least part of the gate reset lines extend in a same direction as the first anode reset lines and/or the second anode reset lines, and the gate reset lines are disposed adjacent to the first anode reset lines and/or the second anode reset lines, the gate reset lines and the first anode reset lines or the second anode reset lines provide signals of different rows and/or columns.

39. The display panel according to claim 37 , wherein

the gate reset lines and the first anode reset lines or the second anode reset lines provide signals of adjacent rows and/or columns.

40. The display panel according to claim 37 , wherein

when the gate reset lines are disposed adjacent to the first anode reset lines and the second anode reset lines, the first anode reset lines and the second anode reset lines are located on a same side of the gate reset lines.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2023

From: LI, RUI

To: WUHAN TIANMA MICRO-ELECTRONICS CO., LTD.

Reel/Frame 064408/0786 →

Priority Claims (1)

CN 202310550277.0 · May 16, 2023 · national

Continuity (1)

Related Publication 20240021149A1 · Jan 18, 2024

References Cited (5)

US 20220335894A1 · Zhou · 2022 [cited by examiner]

CN 110223633B · 2021 [cited by applicant]

CN 114743507A · 2022 [cited by applicant]

CN 115909944A · 2023 [cited by applicant]

Office Action mailed Jun. 23, 2025, issued in corresponding Chinese Application No. 202310550277.0, filed May 16, 2023, 20 pages. [cited by applicant]