Replacement gate process for semiconductor devices
Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and gate stacks over the substrate, wherein each of the gate stacks includes an electrode layer, a first hard mask (HM) layer over the electrode layer, and a second HM layer over the first HM layer. The method further includes depositing a dielectric layer over the substrate and the gate stacks and filling spaces between the gate stacks; and performing a first chemical mechanical planarization (CMP) process to partially remove the dielectric layer. The method further includes performing an etching process to remove the second HM layer and to partially remove the dielectric layer, thereby exposing the first HM layer. The method further includes performing a second CMP process to at least partially remove the first HM layer.
1 . A method comprising:
forming a first gate stack and a second gate stack over a substrate, wherein the first and second gate stacks each includes a gate electrode layer and a first layer disposed on the gate electrode layer, wherein the second gate stack is taller than the first gate stack;
depositing an etch stop layer over top surfaces of the first gate stack, the second gate stack and the substrate as well as sidewalls of the first gate stack and the second gate stack;
forming a dielectric layer over the etch stop layer;
performing a first removal process to remove a first portion of the dielectric layer over the first and second gate stacks, wherein a second portion of the of the dielectric layer is disposed directly over the first gate stack while no portions of the dielectric layer are disposed directly over the second gate stack after the performing of the first removal process, wherein the first removal process includes applying a first removal material to remove the first portion of the dielectric layer from over the first and second gate stacks;
performing a second removal process to expose the first layer in the first and second gate stacks such that top surfaces of the first layer and the dielectric layer are lower than topmost surface of the etch stop layer, wherein the second removal process includes applying a second removal material to expose the first layer in the first and second gate stacks, the second removal material having a different material composition than the first removal material; and
after performing the second removal process, performing a gate replacement process on the first gate stack by replacing the first layer and the gate electrode layer in the first gate stack with at least another gate electrode layer.
2 . The method of claim 1 , wherein the performing of the gate replacement process on the first gate stack by replacing the first layer and the gate electrode layer in the first gate stack with at least another gate electrode layer includes:
removing a first portion of the gate electrode layer to thereby create a space between a second portion and a third portion of the gate electrode layer; and
forming a dielectric layer in the space to thereby electrically isolate the second portion and the third portion of the gate electrode layer.
3 . The method of claim 1 , wherein the performing of the first removal process includes performing a planarization process.
4 . The method of claim 1 , wherein the performing of the second removal process includes performing an etching process.
5 . The method of claim 1 , wherein the first gate stack further includes a second layer disposed directly on the first layer, the second layer formed of a different material than the second layer, and
wherein the second layer is removed during the performing of the second removal process to expose the first layer.
6 . The method of claim 5 , wherein the performing of the second removal process to expose the first layer in the first and second gate stacks includes:
performing a first etching process to remove a first portion of the second layer from the first gate stack; and
performing a second etching process to remove a second portion of the second layer to expose the first layer in the first gate stack.
7 . The method of claim 5 , wherein the first layer is a nitrogen-containing material layer, and
wherein the second layer is an oxygen-containing material layer.
8 . A method comprising:
providing a first gate stack and a second gate stack over a substrate, wherein the first and second gate stacks each includes a gate electrode layer, a first layer disposed over the gate electrode layer and a second layer disposed over the first layer, wherein the second gate stack is shorter than the first gate stack;
forming a first dielectric layer directly on the second layer of the first and second gate stacks;
forming a second dielectric layer directly on the first dielectric layer;
removing a first portion of the second dielectric layer to expose the first dielectric layer over the first gate stack while a second portion of the second dielectric layer covers the first dielectric layer disposed over the second gate stack; and
removing the second portion of the second dielectric layer and the first dielectric layer over the first and second gate stacks to expose the second layer in the first and second gate stacks, wherein the first and second gate stacks extend to the same height above the substrate after the removing of the second portion of the second dielectric layer and the first dielectric layer over the first and second gate stacks.
9 . The method of claim 8 , further comprising removing the exposed second layer from the first and second gate stacks to expose the gate electrode layer in the first and second gate stacks.
10 . The method of claim 9 , further comprising:
removing a portion of the gate electrode layer in the first gate stack to thereby form a first trench and removing a portion of the gate electrode layer in the second gate stack to thereby form a second trench; and
forming a dielectric isolation material in the first and second trenches, the dielectric isolation material interfacing with remaining portions of the gate electrode layer in the first and second gate stacks.
11 . The method of claim 10 , further comprising replacing the remaining portions of the gate electrode layer in the first and second gate stacks with a metal gate layer in the first and second gate stack.
12 . The method of claim 8 , wherein the removing of the first portion of the second dielectric layer includes performing a first removal process using a first removal material, and
wherein the removing of the second portion of the second dielectric layer and the first dielectric layer includes performing a second removal process using a second removal material, and
wherein the second removal process is different than the first removal process and the second removal material is different than the first removal material.
13 . The method of claim 12 , wherein the first removal process includes a chemical mechanical planarization process and the second removal process includes an etching process.
14 . The method of claim 8 , wherein the first layer is a nitrogen-containing material layer, and
wherein the second layer is an oxygen-containing material layer.
15 . The method of claim 8 , wherein the first gate stack has a first width and the second gate stack has a second width that is different than the first width after the providing of first gate stack and the second gate stack over the substrate.
16 . The method of claim 8 , further comprising removing the exposed second layer from the first and second gate stacks to expose the gate electrode layer in the first and second gate stacks,
wherein the first dielectric layer extends to a first height above the substrate after the removing of the exposed second layer from the first and second gate stacks, and
wherein the second dielectric layer extends to a second height above the substrate after the removing of the exposed second layer from the first and second gate stacks, the second height being less than the first height.
17 . A method comprising:
providing a first gate stack and a second gate stack over a substrate, wherein the first and second gate stacks each includes a gate electrode layer, a first layer disposed over the gate electrode layer and a second layer disposed over the first layer, wherein the second gate stack is shorter than the first gate stack;
forming a first dielectric layer directly on the first and second gate stacks;
removing the first dielectric layer over the first gate stack and the second gate stack to expose the second layer in the first and second gate stacks;
removing the exposed second layer from the first and second gate stacks to expose the first layer in the first and second gate stacks, wherein the first dielectric layer disposed on the first and second gate stacks extends to a greater height above the substrate than the first layer after the removing of the exposed second layer from first and second gate stacks to expose the first layer in the first and second gate stacks; and
removing the exposed first layer from the first and second gate stacks to expose the gate electrode layer in the first and second gate stacks.
18 . The method of claim 17 , wherein the removing of the first dielectric layer over the first gate stack and the second gate stack to expose the second layer in the first and second gate stacks includes performing a first etching process using a first etchant, and
wherein the removing of the exposed second layer from the first and second gate stacks to expose the first layer in the first and second gate stacks includes performing a second etching process using a second etchant that has a different material composition than the first etchant.
19 . The method of claim 17 , further comprising forming a second dielectric layer directly on the first dielectric layer prior to removing the first dielectric layer over the first gate stack and the second gate stack to expose the second layer in the first and second gate stacks.
20 . The method of claim 17 , further comprising after removing the exposed first layer from the first and second gate stacks, performing a gate replacement process on the first and second gate stacks by replacing the gate electrode layer in the first and second gate stacks with at least another gate electrode layer.