Ferroelectric memory and storage device
A ferroelectric memory includes at least one storage cell. Each storage cell includes a transistor, a first ferroelectric capacitor, and at least one voltage divider capacitor. The transistor includes a gate electrode, a source electrode, and a drain electrode. One electrode of the first ferroelectric capacitor is connected to the gate electrode. The other electrode of the first ferroelectric capacitor is connected to a word line. One electrode of each voltage divider capacitor in the at least one voltage divider capacitor is connected to the gate electrode, and the other electrode of each voltage divider capacitor in the at least one voltage divider capacitor is connected to the source electrode.
1 . A ferroelectric memory, comprising:
at least one storage cell, wherein each storage cell comprises:
a transistor, comprising a gate electrode, a source electrode, and a drain electrode;
a first ferroelectric capacitor, comprising a first electrode and a second electrode, wherein the first electrode of the first ferroelectric capacitor is coupled to the gate electrode, and the second electrode of the first ferroelectric capacitor is coupled to a word line; and
at least one voltage divider capacitor, comprising:
a first electrode and a second electrode, wherein the first electrode of each voltage divider capacitor is separately coupled to the gate electrode, and the second electrode of each voltage divider capacitor is separately coupled to the source electrode; and
at least one first capacitor, wherein the first capacitor is a high-dielectric-constant capacitor; and at least one second capacitor, wherein the second capacitor is a ferroelectric capacitor.
2 . The ferroelectric memory of claim 1 , wherein the voltage divider capacitor is a high-dielectric-constant capacitor.
3 . The ferroelectric memory of claim 1 , wherein the voltage divider capacitor is a ferroelectric capacitor, and a dielectric material of the ferroelectric capacitor comprises a ferroelectric material.
4 . The ferroelectric memory of claim 1 , wherein the ferroelectric memory further comprises:
a bit line, coupled to the drain electrode;
a source line, coupled to the source electrode; and
the word line, coupled to the second electrode of the first ferroelectric capacitor.
5 . The ferroelectric memory of claim 1 , wherein the ferroelectric memory further comprises:
a first voltage line, wherein a first end of the first voltage line is coupled to the source electrode, and a second end of the first voltage line is coupled to a controller;
a second voltage line, wherein a first end of the second voltage line is coupled to the drain electrode, and a second end of the second voltage line is coupled to the controller; and
a third voltage line, wherein a first end of the third voltage line is coupled to the second electrode of the first ferroelectric capacitor, and a second end of the third voltage line are coupled to the controller.
6 . The ferroelectric memory of claim 5 , wherein the at least one storage cell comprises:
a first storage cell, wherein when data is written into the first storage cell, a voltage difference between the first voltage line and the second voltage line of the first storage cell is 0, and an absolute value of a voltage difference between the third voltage line and the second voltage line of the first storage cell is equal to a first specified voltage.
7 . The ferroelectric memory of claim 6 , wherein the at least one storage cell further comprises:
a second storage cell, wherein when the data is written into the first storage cell, an absolute value of a voltage difference between the third voltage line and the second voltage line of the second storage cell is less than one half of the first specified voltage.
8 . The ferroelectric memory of claim 6 , wherein when the data is written into the first storage cell, the first voltage line, the second voltage line, and the third voltage line of a second storage cell in the at least one storage cell are all in a floating state.
9 . The ferroelectric memory of claim 6 , wherein when the data is written into the first storage cell, bias voltages of the first voltage line, the second voltage line, and the third voltage line of a second storage cell in the at least one storage cell are all one half of the first specified voltage.
10 . The ferroelectric memory of claim 6 , wherein when the data is read from the first storage cell in the at least one storage cell, a bias voltage of the first voltage line of the first storage cell is 0, a bias voltage of the second voltage line of the first storage cell is a second specified voltage, and a bias voltage of the third voltage line of the first storage cell is a third specified voltage.
11 . The ferroelectric memory of claim 5 , wherein when the data is read from the first storage cell in the at least one storage cell, the third voltage line of a second storage cell in the at least one storage cell is in the floating state or grounded.
12 . The ferroelectric memory of claim 5 , wherein when the data is read from the first storage cell in the at least one storage cell, the bias voltages of the first voltage line and the second voltage line of a second storage cell in the at least one storage cell are both 0.
13 . A storage device, wherein the storage device comprises:
a controller, configured to control reading and writing of a ferroelectric memory; and
the ferroelectric memory, comprising:
at least one storage cell, wherein each storage cell comprises:
a transistor, comprising a gate electrode, a source electrode, and a drain electrode;
a first ferroelectric capacitor, comprising a first electrode and a second electrode, wherein the first electrode of the first ferroelectric capacitor is coupled to the gate electrode, and the second electrode of the first ferroelectric capacitor is coupled to a word line; and
at least one voltage divider capacitor, comprising a first electrode and a second electrode, wherein
the first electrode of each voltage divider capacitor is separately coupled to the gate electrode, and the second electrode of each voltage divider capacitor is separately coupled to the source electrode; and
at least one first capacitor, wherein the first capacitor is a high-dielectric-constant capacitor; and at least one second capacitor, wherein the second capacitor is a ferroelectric capacitor.
14 . The storage device of claim 13 , wherein the voltage divider capacitor is a high-dielectric-constant capacitor.
15 . The storage device of claim 13 , wherein the voltage divider capacitor is a ferroelectric capacitor, and a dielectric material of the ferroelectric capacitor comprises a ferroelectric material.
16 . The storage device of claim 13 , wherein the ferroelectric memory further comprises:
a bit line, coupled to the drain electrode;
a source line, coupled to the source electrode; and
the word line, coupled to the second electrode of the first ferroelectric capacitor.
17 . The storage device of claim 13 , wherein the ferroelectric memory further comprises:
a first voltage line, wherein a first end of the first voltage line is coupled to the source electrode, and a second end of the first voltage line is coupled to a controller;
a second voltage line, wherein a first end of the second voltage line is coupled to the drain electrode, and a second end of the second voltage line is coupled to the controller; and
a third voltage line, wherein a first end of the third voltage line is coupled to the second electrode of the first ferroelectric capacitor, and a second end of the third voltage line are coupled to the controller.
18 . The storage device of claim 17 , wherein the at least one storage cell comprises:
a first storage cell, wherein when data is written into the first storage cell, a voltage difference between the first voltage line and the second voltage line of the first storage cell is 0, and an absolute value of a voltage difference between the third voltage line and the second voltage line of the first storage cell is equal to a first specified voltage.