Semiconductor memory devices and methods of manufacturing thereof
View Patent ↗A method for fabricating memory devices includes forming a first portion of a memory device that includes a first device portion and one or more first interface portions. The first device portion includes a plurality of first memory strings, each of which includes a plurality of first memory cells vertically separated from one another. Each of the one or more first interface portions, laterally abutted to one side of the first device portion, includes a plurality of first word lines (WLs). The method further includes forming a plurality of first source lines (SLs) and a plurality of first bit lines (BLs) in the first device portion. The method further includes forming a first seal ring structure that laterally encloses both the first device portion and the first interface portion concurrently with forming the pluralities of SLs and BLs.
1. A method for fabricating memory devices, comprising:
forming a first memory device that includes a plurality of first memory cells arranged along a vertical direction to a surface of a substrate; and
forming a plurality of first source lines (SLs) and a plurality of first bit lines (BLs) extending along the vertical direction, each of the first SLs and each of the first BLs extending through a respective set of the first memory cells; and
concurrently with forming the first SLs and first BLs, forming a first seal ring structure that laterally encloses the first memory device.
2. The method of claim 1 , wherein the first SLs, the first BLs, and the first seal ring structure each essentially consist of a continuously formed metal material.
3. The method of claim 1 , wherein the first SLs, the first BLs, and the first seal ring structure each essentially consist of a continuously formed semiconductor material.
4. The method of claim 1 , wherein the first seal ring structure is laterally spaced apart from the first memory device with an intermetal dielectric (IMD) material.
5. The method of claim 1 , concurrently with forming the first seal ring structure, further comprising forming a second seal ring structure that laterally encloses the first seal ring structure.
6. The method of claim 5 , wherein the second seal ring structure is formed of the same material as a material of the first SLs, the first BLs, and the first seal ring structure.
7. The method of claim 1 , prior to forming the first memory device, further comprising:
forming a plurality of transistors over a substrate;
forming a plurality of metallization levels over the plurality of transistors, wherein each of the plurality of metallization levels includes a plurality of interconnect structures electrically coupled to one or more of the plurality of transistors.
8. The method of claim 7 , further comprising:
forming, over a topmost one of the plurality of metallization levels, a stack of insulation layers and sacrificial layers alternately disposed on top of one another;
patterning a portion of the stack to have a staircase profile along at least one of sides of the portion of the stack;
replacing portions of the plurality of sacrificial layers to form a plurality of WLs that have the staircase profile, wherein each of the WLs laterally extend through the portion of the stack.
9. The method of claim 8 , further comprising:
forming a plurality of first memory layers that each vertically extend through the portion of the stack;
forming a plurality of semiconductor channel films that each vertically extend through the portion of the stack, wherein each of the semiconductor channel films is coupled to respective ones of the WLs through a respective one of the first memory layers to partially form one of a plurality of memory strings.
10. The method of claim 1 , further comprising:
forming a second memory device that includes a plurality of second memory cells arranged along the vertical direction; and
concurrently with forming the first seal ring structure, forming a plurality of second SLs and a plurality of second BLs extending along the vertical direction, each of the second SLs and each of the second BLs extending through a respective set of the second memory cells.
11. The method claim 10 , concurrently with forming the first seal ring structure, further comprising forming a third seal ring structure that laterally encloses the second memory device.
12. The method of claim 11 , wherein the first seal ring structure and the third seal ring structure are separated apart from each other.
13. A method for fabricating memory devices, comprising:
forming a first memory device that includes a plurality of first memory cells arranged along a vertical direction to a surface of a substrate;
forming a plurality of first source lines (SLs) and a plurality of first bit lines (BLs) extending along the vertical direction, each of the first SLs and each of the first BLs extending through a respective set of the first memory cells; and
concurrently with forming the first SLs and first BLs, forming a first seal ring structure that laterally encloses the first memory device;
wherein the first SLs, the first BLs, and the first seal ring structure each include a metal material.
14. The method of claim 13 , wherein the first seal ring structure is laterally spaced apart from the first memory device with an intermetal dielectric (IMD) material.
15. The method of claim 13 , concurrently with forming the first seal ring structure, further comprising forming a second seal ring structure that laterally encloses the first seal ring structure.
16. The method of claim 15 , wherein the second seal ring structure is formed of the same material as a material of the first SLs, the first BLs, and the first seal ring structure.
17. The method of claim 13 , further comprising:
forming a second memory device that includes a plurality of second memory cells arranged along the vertical direction; and
concurrently with forming the first seal ring structure, forming a plurality of second SLs and a plurality of second BLs extending along the vertical direction, each of the second SLs and each of the second BLs extending through a respective set of the second memory cells.
18. The method of claim 17 , further comprising:
concurrently with forming the first seal ring structure, further comprising forming a third seal ring structure that laterally encloses the second memory device;
wherein the first seal ring structure and the third seal ring structure are separated apart from each other.
19. A method for fabricating memory devices, comprising:
forming a first memory device that includes a plurality of first memory cells arranged along a vertical direction;
forming a second memory device that includes a plurality of second memory cells arranged along the vertical direction;
forming a plurality of first source lines (SLs) and a plurality of first bit lines (BLs) extending along the vertical direction, each of the first SLs and each of the first BLs extending through a respective set of the first memory cells;
forming a plurality of second SLs and a plurality of second BLs extending along the vertical direction, each of the second SLs and each of the second BLs extending through a respective set of the second memory cells; and
concurrently with forming the first SLs, first BLs, second SLs, and second BLs, forming a first seal ring structure that laterally encloses the first memory device and a second seal ring structure that laterally encloses the second memory device.
20. The method of claim 19 , wherein the first SLs, the first BLs, the second SLs, the second BLs, the first seal ring structure, and the second seal ring structure are formed of a same material.