IP Library › Granted Patent US 12,451,166
Granted Patent B2
US 12,451,166 · App. 18/365,726 · Granted Oct 21, 2025

Semiconductor device and method of manufacturing semiconductor device

Inventors: Yong Jin Jeong (Icheon, KR); Sang Gu Yeo (Icheon, KR)
Assignee: SK hynix Inc.
G11C5/063H10B63/84H10N70/021H10N70/841
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,451,166
App. No.
18/365,726
Granted
Oct 21, 2025
Kind
B2
Abstract

A semiconductor device may include a first contact plug, a word line electrically connected to the first contact plug and extending in a first direction, a second contact plug, a bit line extending in a second direction that intersects the first direction, and a memory cell disposed between the word line and the bit line and including a variable resistance layer. The bit line may include a first protruding part that protrudes into the memory cell, a second protruding part that is connected to the second contact plug, and a connection part that connects the first protruding part and the second protruding part and that extends in the second direction.

Claims (41)

1. A semiconductor device comprising:

a first contact plug;

a word line electrically connected to the first contact plug and extending in a first direction;

a second contact plug;

a bit line extending in a second direction that intersects the first direction; and

a memory cell disposed between the word line and the bit line and comprising a variable resistance layer,

wherein the bit line comprises a first protruding part that protrudes into the memory cell, a second protruding part that is connected to the second contact plug, and a connection part that connects the first protruding part and the second protruding part and that extends in the second direction.

2. The semiconductor device of claim 1 , wherein the variable resistance layer surrounds a sidewall and a bottom of the first protruding part.

3. The semiconductor device of claim 1 , wherein the memory cell further comprises an electrode layer disposed between the variable resistance layer and the first protruding part.

4. The semiconductor device of claim 1 , wherein the first protruding part comprises:

a first conductive layer disposed within the variable resistance layer;

a barrier layer disposed within the first conductive layer; and

a second conductive layer disposed within the barrier layer.

5. The semiconductor device of claim 1 , wherein the second protruding part comprises:

a barrier layer, and

a second conductive layer disposed within the barrier layer.

6. The semiconductor device of claim 1 , wherein the connection part comprises:

a first conductive layer;

a barrier layer disposed on the first conductive layer; and

a second conductive layer disposed on the barrier layer.

7. The semiconductor device of claim 1 , further comprising a separation insulating layer disposed on the second contact plug,

wherein the second protruding part is electrically connected to the second contact plug and extends through the separation insulating layer.

8. A method of manufacturing a semiconductor device, comprising:

forming a first contact plug;

forming a word line connected to the first contact plug and extending in a first direction;

forming a second contact plug;

forming a separation insulating layer on the second contact plug;

forming a first opening within the word line;

forming a second opening that exposes the second contact plug through the separation insulating layer; and

forming a bit line comprising a first protruding part extending in a second direction and disposed within the first opening, a second protruding part disposed within the second opening, and a connection part connecting the first protruding part and the second protruding part, the second direction intersecting the first direction.

9. The method of claim 8 , further comprising forming a variable resistance layer within the first opening.

10. The method of claim 9 , wherein the forming of the variable resistance layer comprises forming the variable resistance layer along an inner side of the first opening with a thickness sufficient to partially fill the first opening.

11. The method of claim 8 , further comprising forming a first conductive layer within the first opening before forming the second opening.

12. The method of claim 11 , wherein the forming of the first conductive layer comprises forming the first conductive layer along an inner side of the first opening with a thickness to partially fill the first opening.

13. The method of claim 8 , wherein the forming of the second opening comprises forming the second opening when the first opening has been at least partially filled.

14. The method of claim 8 , wherein the forming of the bit line comprises:

forming a second conductive layer along inner sides of the first opening and the second opening; and

forming the bit line by patterning the second conductive layer.

15. The method of claim 14 , further comprising forming a barrier layer before forming the second conductive layer.

16. The method of claim 8 , wherein the second protruding part of the bit line is electrically connected to the second contact plug.

17. The method of claim 8 , wherein when the first contact plug is formed, the second contact plug is formed.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 7, 2023
From: JEONG, YONG JIN; YEO, SANG GU
To: SK HYNIX INC.
Reel/Frame 064515/0013 →
Priority Claims (1)
KR 10-2023-0045257 · Apr 6, 2023 · national
Continuity (1)
Related Publication 20240339135A1 · Oct 10, 2024
References Cited (4)
US 8344345B2 · Mikawa et al. · 2013 [cited by applicant]
US 20090230378A1 · Ryoo · 2009 [cited by examiner]
US 20120256152A1 · Kakegawa · 2012 [cited by examiner]
KR 1020050002004A · 2005 [cited by applicant]