Storage apparatus and method of controlling storage controller
A frontend interface of a controller according to the present invention includes a plurality of corresponding queueing interfaces for each processor of the controller, and an enqueueing destination of a host I/O command can be switched in response to an instruction from a processor. When a controller OS restarts, the controller waits for completion of a host I/O and executes controller blocking and restarting during setup. Therefore, to determine whether or not this process is possible, the processor gives an instruction to switch a queue and waits until a switch source queue is empty.
1. A storage apparatus that processes a request from a host apparatus, the storage apparatus comprising a plurality of storage controllers,
wherein a first storage controller in the plurality of storage controllers includes
a first frontend interface that controls a protocol of communication with the host apparatus, and
a first processor that controls the storage apparatus,
wherein a second storage controller in the plurality of storage controllers includes a second processor that controls the storage apparatus,
wherein the first storage controller further includes
a first address translation unit that executes translation between a first address used by the first processor and a second address used by the first frontend interface,
a second address translation unit that executes translation between a third address used by the second processor and the second address used by the first frontend interface,
a first outbound queue that controls data transfer from the first frontend interface to the first processor through the first address translation unit, and
a first inbound queue that controls data transfer from the first processor to the first frontend interface through the first address translation unit,
wherein the second storage controller further includes
a second outbound queue that controls data transfer from the first frontend interface to the second processor through the second address translation unit, and
a second inbound queue that controls data transfer from the second processor to the first frontend interface through the second address translation unit, and
wherein the first frontend interface receives a first enqueueing destination switch instruction to designate the second outbound queue as an enqueueing destination of a request from the host apparatus and then switches an enqueueing destination to the second outbound queue from a request which comes from the host apparatus and to which an identifier of a series of operations related to a subsequently received new host request is given.
2. The storage apparatus according to claim 1 , wherein the first processor
sends the first enqueueing destination switch instruction to the first frontend interface before a process is stopped, and
stops the process after the first outbound queue and the first inbound queue are empty.
3. The storage apparatus according to claim 2 , wherein the first processor stops the process when an identifier of a series of operations related to a request which comes from the host apparatus and which is recently processed with the first outbound queue and an identifier of a series of operations related to a host request to a response recently processed with the first inbound queue among responses to requests from the host apparatus indicate the same host request.
4. The storage apparatus according to claim 1 , wherein the first frontend interface
individually sets a transfer destination address of a first interrupt related to the first outbound queue and a transfer destination address of a second interrupt related to the second outbound queue,
sends the first interrupt to the first processor through the first address translation unit, and
sends the second interrupt to the second processor through the second address translation unit.
5. The storage apparatus according to claim 1 , wherein the first processor is able to read an enqueueing destination setting of the first frontend interface.
6. The storage apparatus according to claim 5 , wherein the first processor switches an enqueueing destination to the first outbound queue when the enqueueing destination is the second outbound queue result obtained by reading the enqueueing destination setting of a request from the host apparatus from the first frontend interface after restart.
7. The storage apparatus according to claim 1 , further comprising:
a third address translation unit that executes translation between the first address used by the first processor and a fourth address used by a second frontend interface; and
a fourth address translation unit that executes translation between the third address used by the second processor and a fourth address used by the second frontend interface,
wherein the first and second processors communicate with each other through the third and fourth address translation units.
8. The storage apparatus according to claim 1 ,
wherein a switch including the first and second address translation units is included, and
wherein the first and second processors communicate with each other through the switch.
9. The storage apparatus according to claim 1 ,
wherein the first frontend interface enqueues a request from the host apparatus to the first or second outbound queue before the first enqueueing destination switch instruction is received,
wherein the first processor sends the first enqueueing destination switch instruction to the first frontend interface before the process is stopped,
wherein, when the first enqueueing destination switch instruction is received from the first processor, the first frontend interface enqueues requests in only the second outbound queue from a request from the host apparatus to which an identifier of a series of operations related to a subsequently received new host request is given, and
wherein the first processor stops the process after the first outbound queue and the first inbound queue are empty.
10. The storage apparatus according to claim 9 ,
wherein the second storage controller further includes
a second frontend interface that controls a protocol of communication with the host apparatus,
a third address translation unit that executes translation between the first address used by the first processor and a fourth address used by the second frontend interface,
a fourth address translation unit that executes translation between the third address used by the second processor and a fourth address used by the second frontend interface,
a third outbound queue that controls data transfer from the second frontend interface to the second processor through the fourth address translation unit, and
a third inbound queue that executes data transfer from the second processor to the second frontend interface through the fourth address translation unit,
wherein the first storage controller further includes
a fourth outbound queue that controls data transfer from the second frontend interface to the first processor through the third address translation unit, and
a fourth inbound queue that controls data transfer from the first processor to the second frontend interface through the third address translation unit,
wherein the second frontend interface enqueues a request from the host apparatus in the third or fourth outbound queue,
wherein the second processor sends a second enqueueing destination switch instruction to designate the third outbound queue as an enqueueing destination of a request from the host apparatus to the second frontend interface before the first processor stops the process,
wherein, when the second enqueueing destination switch instruction is received, the second frontend interface enqueues requests in only the third outbound queue from a request from the host apparatus to which an identifier of a series of operations related to a subsequently received new host request is given, and
wherein the first processor stops the process after the first outbound queue, the first inbound queue, the fourth outbound queue, and the fourth inbound queue are empty.
11. The storage apparatus according to claim 10 ,
wherein an identifier of a series of operations related to a request which comes from the host apparatus and which is recently processed with the first outbound queue and an identifier of a series of operations related to a host request to a response recently processed with the first inbound queue among responses to requests from the host apparatus indicate the same host request, and
wherein the first processor stops the process when an identifier of a series of operations related to a request which comes from the host apparatus and which is recently processed with the fourth outbound queue and an identifier of a series of operations related to a host request to a response recently processed with the fourth inbound queue among responses to requests from the host apparatus indicate the same host request.
12. The storage apparatus according to claim 1 , wherein, when a failure occurs in the first storage controller, the second processor detecting the failure sends the first enqueueing destination switch instruction to the first frontend interface.
13. A method of controlling storage controllers of a storage apparatus that processes a request from a host apparatus,
wherein the storage apparatus includes a plurality of storage controllers,
wherein a first storage controller in the plurality of storage controllers includes
a first frontend interface that controls a protocol of communication with the host apparatus, and
a first processor that controls the storage apparatus,
wherein a second storage controller in the plurality of storage controllers includes a second processor that controls the storage apparatus,
wherein the first storage controller further includes
a first address translation unit that executes translation between a first address used by the first processor and a second address used by the first frontend interface,
a second address translation unit that executes translation between a third address used by the second processor and the second address used by the first frontend interface,
a first outbound queue that controls data transfer from the first frontend interface to the first processor through the first address translation unit, and
a first inbound queue that controls data transfer from the first processor to the first frontend interface through the first address translation unit,
wherein the second storage controller further includes
a second outbound queue that controls data transfer from the first frontend interface to the second processor through the second address translation unit, and
a second inbound queue that controls data transfer from the second processor to the first frontend interface through the second address translation unit, and
wherein the method comprises:
receiving, by the first frontend interface, a first enqueueing destination switch instruction to designate the second outbound queue as an enqueueing destination of a request from the host apparatus; and
switching, by the first frontend interface, an enqueueing destination to the second outbound queue from a request which comes from the host apparatus and to which an identifier of a series of operations related to a subsequently received new host request is given after receiving the first enqueueing destination switch instruction.