IP Library › Granted Patent US 12,405,752
Granted Patent B2
US 12,405,752 · App. 18/373,234 · Granted Sep 2, 2025

Migrating data between byte-addressable and block-addressable storage devices in processor-based devices

Inventor: Andrew Mills (Coto de Caza, CA)
Assignee: SMART Modular Technologies, Inc.
G06F3/0664G06F3/0619G06F3/0653G06F3/0659G06F3/0673
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Quick Facts
Patent No.
US 12,405,752
App. No.
18/373,234
Granted
Sep 2, 2025
Kind
B2
Abstract

Migrating data between byte-addressable and block-addressable storage devices in processor-based devices is disclosed. In this regard, a processor of a processor-based device is communicatively coupled to both a byte-addressable storage device and a block-addressable storage device. The processor is configured to present the byte-addressable storage device and the block-addressable storage device as a single virtual storage device (i.e., as either a byte-addressable virtual device or a block-addressable virtual storage device). The processor is further configured to identify a low-activity region in the byte-addressable storage device, and to also identify a high-activity region in the block-addressable storage device. The processor then exchanges a first storage region corresponding to the low-activity region and comprising a memory address region of the byte-addressable storage device with a second storage region corresponding to the high-activity region and comprising a block region of the block-addressable storage device.

Claims (75)

1. A processor-based device, comprising a virtualization circuit communicatively coupled to a byte-addressable storage device and a block-addressable storage device;

the virtualization circuit configured to:

present, to a processor of the processor-based device, the byte-addressable storage device and the block-addressable storage device as a single virtual storage device;

generate a usage statistic for each of the byte-addressable storage device and the block-addressable storage device;

identify a low-activity region in the byte-addressable storage device based on the usage statistic for the byte-addressable storage device;

identify a high-activity region in the block-addressable storage device based on the usage statistic for the block-addressable storage device; and

exchange a first storage region corresponding to the low-activity region and comprising a memory address region of the byte-addressable storage device with a second storage region corresponding to the high-activity region and comprising a block region of the block-addressable storage device;

wherein:

the single virtual storage device is configurably presented as one of a byte-addressable virtual storage device and a block-addressable virtual storage device;

the high-activity region comprises a block-addressable storage region for which the corresponding usage statistic exceeds a value of a promotion threshold; and

the low-activity region comprises a byte-addressable storage region for which the corresponding usage statistic is lower than the usage statistic for the high-activity region.

2. The processor-based device of claim 1 , wherein:

the virtualization circuit comprises a translation table; and

the virtualization circuit is configured to exchange the first storage region with the second storage region by being configured to:

copy the low-activity region to a first reserved section located in the block-addressable storage device using a byte-based read command to read from the byte-addressable storage device and a block-based write command to write to the block-addressable storage device;

update a physical address of the low-activity region in the translation table;

copy the high-activity region to a second reserved section located in the byte-addressable storage device using a block-based read command to read from the block-addressable storage device and a byte-based write command to write to the byte-addressable storage device; and

update a physical address of the high-activity region in the translation table.

3. The processor-based device of claim 2 , wherein:

the virtualization circuit is configured to copy the low-activity region by being configured to convert from a byte format to a block format without losing data; and

the virtualization circuit is configured to copy the high-activity region by being configured to convert from a block format to a byte format without losing data.

4. The processor-based device of claim 1 , wherein:

the virtualization circuit is further configured to receive, from the processor, a data access command to access the high-activity region; and

the virtualization circuit is configured to identify the low-activity region, identify the high-activity region, and exchange the first storage region with the second storage region responsive to receiving the data access command.

5. The processor-based device of claim 4 , wherein:

the virtual storage device comprises a byte-addressable virtual device; and

the data access command comprises a byte-based storage command.

6. The processor-based device of claim 4 , wherein:

the virtual storage device comprises a block-addressable virtual device; and

the data access command comprises a block-based storage command.

7. The processor-based device of claim 1 , wherein the virtualization circuit is configured to identify the low-activity region, identify the high-activity region, and exchange the first storage region with the second storage region at periodic time intervals.

8. The processor-based device of claim 1 , wherein the promotion threshold comprises one or more of an access frequency threshold, a data access latency threshold, an endurance threshold, and an access request size threshold.

9. A method, comprising:

presenting, by a processor of a processor-based device, a byte-addressable storage device and a block-addressable storage device as a single virtual storage device;

generating a usage statistic for each of the byte-addressable storage device and the block-addressable storage device;

identifying, by the processor, a low-activity region in the byte-addressable storage device based on the usage statistic for the byte-addressable storage device;

identifying, by the processor, a high-activity region in the block-addressable storage device based on the usage statistic for the block-addressable storage device; and

exchanging, by the processor, a first storage region corresponding to the low-activity region and comprising a memory address region of the byte-addressable storage device with a second storage region corresponding to the high-activity region and comprising a block region of the block-addressable storage device;

wherein:

the single virtual storage device is configurably presented as one of a byte-addressable virtual storage device and a block-addressable virtual storage device;

the high-activity region comprises a block-addressable storage region for which the corresponding usage statistic exceeds a value of a promotion threshold; and

the low-activity region comprises a byte-addressable storage region for which the corresponding usage statistic is lower than the usage statistic for the high-activity region.

10. The method of claim 9 , wherein exchanging the first storage region with the second storage region comprises:

copying the low-activity region to a first reserved section located in the block-addressable storage device using a byte-based read command to read from the byte-addressable storage device and a block-based write command to write to the block-addressable storage device;

updating a physical address of the low-activity region in a translation table;

copying the high-activity region to a second reserved section located in the byte-addressable storage device using a block-based read command to read from the block-addressable storage device and a byte-based write command to write to the byte-addressable storage device; and

updating a physical address of the high-activity region in the translation table.

11. The method of claim 10 , wherein:

copying the low-activity region comprises converting from a byte format to a block format without losing data; and

copying the high-activity region comprises converting from a block format to a byte format without losing data.

12. The method of claim 9 , further comprising receiving, by the processor, a data access command to access the high-activity region;

wherein the method comprises identifying the low-activity region, identifying the high-activity region, and exchanging the first storage region with the second storage region responsive to receiving the data access command.

13. The method of claim 12 , wherein:

the virtual storage device comprises a byte-addressable virtual device; and

the data access command comprises a byte-based storage command.

14. The method of claim 12 , wherein:

the virtual storage device comprises a block-addressable virtual device; and

the data access command comprises a block-based storage command.

15. The method of claim 9 , comprising identifying the low-activity region, identifying the high-activity region, and exchanging the first storage region with the second storage region at periodic time intervals.

16. The method of claim 9 , wherein the promotion threshold comprises one or more of an access frequency threshold, a data access latency threshold, an endurance threshold, and an access request size threshold.

17. A non-transitory computer-readable medium, having stored thereon computer-executable instructions that, when executed, cause a processor of a processor-based device to:

present a byte-addressable storage device and a block-addressable storage device as a single virtual storage device;

generate a usage statistic for each of the byte-addressable storage device and the block-addressable storage device;

identify a low-activity region in the byte-addressable storage device based on the usage statistic for the byte-addressable storage device;

identify a high-activity region in the block-addressable storage device based on the usage statistic for the block-addressable storage device; and

exchange a first storage region corresponding to the low-activity region and comprising a memory address region of the byte-addressable storage device with a second storage region corresponding to the high-activity region and comprising a block region of the block-addressable storage device;

wherein:

the single virtual storage device is configurably presented as one of a byte-addressable virtual storage device and a block-addressable virtual storage device;

the high-activity region comprises a block-addressable storage region for which the corresponding usage statistic exceeds a value of a promotion threshold; and

the low-activity region comprises a byte-addressable storage region for which the corresponding usage statistic is lower than the usage statistic for the high-activity region.

18. The non-transitory computer-readable medium of claim 17 , wherein the computer-executable instructions cause the processor to exchange the first storage region with the second storage region by causing the processor to:

copy the low-activity region to a first reserved section located in the block-addressable storage device using a byte-based read command to read from the byte-addressable storage device and a block-based write command to write to the block-addressable storage device;

update a physical address of the low-activity region in a translation table;

copy the high-activity region to a second reserved section located in the byte-addressable storage device using a block-based read command to read from the block-addressable storage device and a byte-based write command to write to the byte-addressable storage device; and

update a physical address of the high-activity region in the translation table.

Assignments (2)
PATENT SECURITY AGREEMENT Recorded Jun 30, 2025
From: CREELED, INC.; PENGUIN SOLUTIONS CORPORATION (DE); SMART EMBEDDED COMPUTING, INC.; SMART HIGH RELIABILITY SOLUTIONS LLC; SMART MODULAR TECHNOLOGIES, INC.; PENGUIN COMPUTING, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 071755/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2023
From: MILLS, ANDREW
To: SMART MODULAR TECHNOLOGIES, INC.
Reel/Frame 065038/0415 →
Continuity (1)
Related Publication 20250103247A1 · Mar 27, 2025
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