IP Library › Granted Patent US 12,261,705
Granted Patent B2
US 12,261,705 · App. 18/373,268 · Granted Mar 25, 2025

Computing device and computing method for computing packet transmission time

Inventors: Chien-Hsun Liao (HsinChu, TW); Wei-Hsuan Chang (HsinChu, TW)
Assignee: Realtek Semiconductor Corp.
H04L1/203H04L1/1887
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Quick Facts
Patent No.
US 12,261,705
App. No.
18/373,268
Granted
Mar 25, 2025
Kind
B2
Abstract

A computing device includes: a storage circuit, for storing an arbitration interframe space (AIFS) time, at least one expected value of at least one backoff time, a preamble time, a short interframe space (SIFS) time and an acknowledgement (ACK) time; a first computing circuit, for computing a payload time according to a packet length and a packet rate; a second computing circuit, coupled to the storage circuit and the first computing circuit, for computing at least one packet transmission time according to the AIFS time, the at least one expected value of the at least one backoff time, the preamble time, the SIFS time, the ACK time and the payload time; and a third computing circuit, coupled to the second computing circuit, for computing a total packet transmission time according to the at least one packet transmission time and an estimated packet error rate.

Claims (26)

1. A computing device for computing a packet transmission time to select a data rate to improve a performance of the computing device, comprising:

a storage circuit, for storing an arbitration interframe space (AIFS) time, at least one expected value of at least one backoff time, a preamble time, a short interframe space (SIFS) time and an acknowledgement (ACK) time;

a first computing circuit, for computing a payload time according to a packet length and a packet rate;

a second computing circuit, coupled to the storage circuit and the first computing circuit, for computing at least one packet transmission time according to the AIFS time, the at least one expected value of the at least one backoff time, the preamble time, the SIFS time, the ACK time and the payload time; and

a third computing circuit, coupled to the second computing circuit, for computing a total packet transmission time according to the at least one packet transmission time and an estimated packet error rate.

2. The computing device of claim 1 , wherein the AIFS time is a waiting time interval before transmitting a packet, and is a predefined value.

3. The computing device of claim 1 , wherein the at least one backoff time is at least one waiting time interval before transmitting a packet, and is at least one random variable with a probability distribution.

4. The computing device of claim 1 , wherein the at least one expected value of the at least one backoff time is at least one median of the at least one backoff time.

5. The computing device of claim 1 , wherein the preamble time is a predefined value, and is defined in a communication standard.

6. The computing device of claim 1 , wherein the SIFS time is a predefined value, and is defined in a communication standard.

7. The computing device of claim 1 , wherein the ACK time is a predefined value, and is a time interval for receiving an ACK.

8. The computing device of claim 1 , wherein the estimated packet error rate is a function of a plurality of packet error rates.

9. The computing device of claim 8 , wherein the function is an average of the plurality of packet error rates.

10. A computing method for computing a packet transmission time to select a data rate to improve a performance of a computing device, comprising:

storing an arbitration interframe space (AIFS) time, at least one expected value of at least one backoff time, a preamble time, a short interframe space (SIFS) time and an acknowledgement (ACK) time;

computing a payload time according to a packet length and a packet rate;

computing at least one packet transmission time according to the AIFS time, the at least one expected value of the at least one backoff time, the preamble time, the SIFS time, the ACK time and the payload time; and

computing a total packet transmission time according to the at least one packet transmission time and an estimated packet error rate.

11. The computing method of claim 10 , wherein the AIFS time is a waiting time interval before transmitting a packet, and is a predefined value.

12. The computing method of claim 10 , wherein the at least one backoff time is at least one waiting time interval before transmitting a packet, and is at least one random variable with a probability distribution.

13. The computing method of claim 10 , wherein the at least one expected value of the at least one backoff time is at least one median of the at least one backoff time.

14. The computing method of claim 10 , wherein the preamble time is a predefined value, and is defined in a communication standard.

15. The computing method of claim 10 , wherein the SIFS time is a predefined value, and is defined in a communication standard.

16. The computing method of claim 10 , wherein the ACK time is a predefined value, and is a time interval for receiving an ACK.

17. The computing method of claim 10 , wherein the estimated packet error rate is a function of a plurality of packet error rates.

18. The computing method of claim 17 , wherein the function is an average of the plurality of packet error rates.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2023
From: LIAO, CHIEN-HSUN; CHANG, WEI-HSUAN
To: REALTEK SEMICONDUCTOR CORP.
Reel/Frame 065038/0839 →
Priority Claims (1)
TW 111139462 · Oct 18, 2022 · national
Continuity (1)
Related Publication 20240137165A1 · Apr 25, 2024
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