LATERAL HIGH VOLTAGE SCR WITH INTEGRATED NEGATIVE STRIKE DIODE
An SCR with a first semiconductor region and plural concentric semiconductor regions, each surrounding the first semiconductor region. The SCR also includes, surrounded by at least one concentric semiconductor region in the plurality of concentric semiconductor regions, an electrically non-contacted region of a semiconductor type and positioned to modulate a snapback voltage of the silicon controlled rectifier and an electrically-contacted region of the semiconductor type and positioned to provide a diodic response between the at least one concentric semiconductor region in the plurality of concentric semiconductor regions and the electrically-contacted region.
1 . A silicon controlled rectifier (SCR), comprising:
a first semiconductor region;
a second semiconductor region circumscribing the first semiconductor region;
an electrically non-contacted semiconductor region adjacent to a first side of the second semiconductor region;
an electrically contacted semiconductor region adjacent to a second side of the second semiconductor region opposite the first side; and
concentric semiconductor regions surrounding the first and second semiconductor regions, the electrically non-contacted semiconductor region, and the electrically contacted semiconductor region.
2 . The SCR of claim 1 , wherein:
the electrically non-contacted semiconductor region has a first linear shape from a plan perspective; and
the electrically contacted semiconductor region has a second linear shape from the plan perspective, wherein the first linear shape is parallel to the second linear shape.
3 . The SCR of claim 2 , wherein:
the first linear shape has a first dimension parallel to the first side of the second semiconductor region; and
the second linear shape has a second dimension parallel to the second side of the second semiconductor region, wherein the first dimension is greater than the second dimension.
4 . The SCR of claim 1 , wherein:
an anode of the SCR is coupled to the first semiconductor region and to the electrically contacted semiconductor region; and
a cathode of the SCR is coupled to the concentric semiconductor regions.
5 . The SCR of claim 1 , further comprising:
a trench region surrounding the concentric semiconductor regions, the trench region including a conductive material.
6 . The SCR of claim 1 , wherein:
the second semiconductor region provides an emitter for a PNP bipolar junction transistor (BJT) of the SCR;
a first concentric semiconductor region of the concentric semiconductor regions provides a collector of the PNP BJT; and
the electrically non-contacted semiconductor region is positioned between the first concentric semiconductor region and the second semiconductor region.
7 . The SCR of claim 1 , wherein:
the first semiconductor region provides a collector for an NPN bipolar junction transistor (BJT) of the SCR;
a second concentric semiconductor region of the concentric semiconductor regions provides an emitter of the NPN BJT; and
the electrically non-contacted semiconductor region is positioned between the first semiconductor region and the second concentric semiconductor region.
8 . The SCR of claim 1 , wherein:
the electrically non-contacted semiconductor region is positioned at a first distance from a first concentric semiconductor region of the concentric semiconductor regions; and
the electrically contacted semiconductor region is positioned at a second distance from the first concentric semiconductor region, the second distance greater than the first distance.
9 . The SCR of claim 8 , wherein the second distance is greater than the first distance by a factor of two to three.
10 . The SCR of claim 8 , wherein:
the electrically non-contacted semiconductor region is positioned at a third distance from a second concentric semiconductor region of the concentric semiconductor regions, the third distance greater than the first distance; and
the electrically contacted semiconductor region is positioned at a fourth distance from the second concentric semiconductor region of the concentric semiconductor regions, the fourth distance greater than the second distance and the third distance.
11 . The SCR of claim 1 , wherein:
a first concentric semiconductor region of the concentric semiconductor regions provides a collector for a PNP bipolar junction transistor (BJT) of the SCR;
a second concentric semiconductor region of the concentric semiconductor regions provides an emitter for an NPN BJT of the SCR; and
the first concentric semiconductor region and the second concentric semiconductor region are in a third concentric semiconductor region of the concentric semiconductor regions.
12 . The SCR of claim 11 , wherein a concentric isolation region is located between the first and second concentric semiconductor regions.
13 . The SCR of claim 1 , wherein:
the electrically non-contacted semiconductor region is configured to facilitate a snapback operation of the SCR; and
the electrically contacted semiconductor region is configured to facilitate a diodic operation of the SCR.
14 . The SCR of claim 13 , wherein the snapback operation includes a breakdown of a junction between a first concentric semiconductor region of the concentric semiconductor regions and an epi layer in which the first concentric semiconductor region is located.
15 . The SCR of claim 13 , wherein the diodic operation includes forward-biasing a diode formed between a first concentric semiconductor region of the concentric semiconductor regions and the electrically contacted semiconductor region.
16 . The SCR of claim 13 , wherein:
the snapback operation is in response to a first electrostatic discharge pulse at the first semiconductor region, the first electrostatic discharge pulse having a first polarity; and
the diodic operation is in response to a second electrostatic discharge pulse at the first semiconductor region, the second electrostatic discharge pulse having a second polarity opposite the first polarity.
17 . A silicon controlled rectifier (SCR), comprising:
an n-type semiconductor region;
a p-type semiconductor region, the p-type semiconductor region circumscribing the n-type semiconductor region;
an n-type electrically non-contacted semiconductor region adjacent to a first side of the p-type semiconductor region;
an n-type electrically contacted semiconductor region adjacent to a second side of the p-type semiconductor region opposite the first side; and
concentric semiconductor regions surround the n-type and p-type semiconductor regions, the n-type electrically non-contacted semiconductor region, and the n-type electrically contacted semiconductor region.
18 . The SCR of claim 17 , wherein:
the n-type electrically non-contacted semiconductor region has a first linear shape from a plan perspective; and
the n-type electrically contacted semiconductor region has a second linear shape from the plan perspective, wherein the first linear shape is parallel to the second linear shape.
19 . The SCR of claim 17 , wherein:
the p-type semiconductor region provides an emitter for a PNP bipolar junction transistor (BJT) of the SCR;
a p-type concentric semiconductor region of the concentric semiconductor regions provides a collector of the PNP BJT; and
the n-type electrically non-contacted semiconductor region is positioned between the p-type concentric semiconductor region and the p-type semiconductor region.
20 . The SCR of claim 17 , wherein:
the n-type semiconductor region provides a collector for an NPN bipolar junction transistor (BJT) of the SCR;
an n-type concentric semiconductor region of the concentric semiconductor regions provides an emitter of the NPN BJT; and
the n-type electrically non-contacted semiconductor region is positioned between the n-type semiconductor region and the n-type concentric semiconductor region.