General-purpose systolic array
A systolic array cell is described, the cell including two general-purpose arithmetic logic units (ALUs) and register-file. A plurality of the cells may be configured in a matrix or array, such that the output of the first ALU in a first cell is provided to a second cell to the right of the first cell, and the output of the second ALU in the first cell is provided to a third cell below the first cell. The two ALUs in each cell of the array allow for processing of a different instruction in each cycle.
1. A processor cell, comprising:
a crossbar switch;
a first floating point logic unit (FPLU) configured to:
receive, as input to the first FPLU, output from the crossbar switch; and
provide, as output from the first FPLU, input to one or more additional processing cells;
a second FPLU configured to:
receive, as input to the second FPLU, output from the crossbar switch; and
provide, as output from the second FPLU, input to the one or more additional processing cells; and
a register file configured to:
receive, as input to the register file, the outputs from the first FPLU and the second FPLU; and
provide, as output from the register file, one or more inputs to the crossbar switch.
2. The processor cell of claim 1 , wherein at least one of the first or second FPLUs comprises an 8-bit, 16-bit, 32-bit, or 64-bit FPLU.
3. The processor cell of claim 1 , wherein the crossbar switch is configured to receive, as input to the crossbar switch, output from the one or more additional processing cells.
4. The processor cell of claim 1 , wherein at least one of the first or second FPLUs comprises a multiplier.
5. The processor cell of claim 1 , further comprising a multiplexer configured to:
receive, as input to the multiplexer, the outputs from the first FPLU and the second FPLU; and
provide, as output from the multiplexer, an input to the register file.
6. The processor cell of claim 1 , wherein the first FPLU is coupled to a first output of the crossbar switch and the second FPLU is coupled to a second output of the crossbar switch.
7. A computation unit, comprising:
a plurality of processor cells having a first output of a first processor cell provided as input to a second processor cell and a second output of the first processor cell provided as input to a third processor cell, wherein each processor cell comprises:
a crossbar switch;
a plurality of floating point logic units (FPLUs), each FPLU configured to:
receive, as input to the FPLU, output from the crossbar switch; and
provide, as output from the FPLU, input to the second or third processor cell; and
a register file configured to:
receive, as input to the register file, the outputs from the plurality of FPLUs; and
provide, as output from the register file, one or more inputs to the crossbar switch.
8. The computation unit of claim 7 , wherein at least one of the plurality of FPLUS comprises an 8-bit, 16-bit, 32-bit, or 64-bit FPLU.
9. The computation unit of claim 7 , wherein at least one of the plurality of processor cells further comprises a multiplexer configured to:
receive, as input to the multiplexer, the outputs from the plurality of FPLUs; and
provide, as output from the multiplexer, an input to the register file.
10. The computation unit of claim 7 , wherein at least one of the plurality of FPLUs comprises a multiplier.
11. The computation unit of claim 7 , wherein the plurality of FPLUs comprises a first FPLU coupled to a first output of the crossbar switch and a second FPLU coupled to a second output of the crossbar switch.
12. The computation unit of claim 7 , wherein a crossbar switch of the first processor cell is configured to receive, as input to the crossbar switch, output from a fourth processor cell.
13. The computation unit of claim 7 , wherein the computation unit is configured to receive two source vectors and produce at least one result vector per cycle.
14. A computing system, comprising:
one or more memories;
one or more processors in communication with the one or more memories;
a plurality of cells in communication with the one or more processors, the plurality of cells having a first output of a first cell provided as input to a second cell and a second output of the first cell provided as input to a third cell, wherein each cell comprises:
a crossbar switch;
a plurality of floating point logic units (FPLUs), each FPLU configured to:
receive, as input to the FPLU, output from the crossbar switch; and
provide, as output from the FPLU, input to the second or third cell;
and a register file configured to:
receive, as input to the register file, the outputs from the plurality of FPLUs; and
provide, as output from the register file, one or more inputs to the crossbar switch.
15. The computing system of claim 14 , wherein the one or more processors comprise at least one of a scalar core or a vector processing unit.
16. The computing system of claim 14 , wherein the one or more memories comprise a vector data cache or a level one cache.
17. The computing system of claim 14 , further comprising a sequencer configured to control instructions sent to the one or more processors and the plurality of cells.
18. The computing system of claim 14 , wherein the plurality of cells is configured to receive two source vectors and produce at least one result vector per cycle.
19. The computing system of claim 14 , wherein at least one of the plurality of cells further comprises a multiplexer configured to:
receive, as input to the multiplexer, the outputs from the plurality of FPLUs; and
provide, as output from the multiplexer, an input to the register file.
20. The computing system of claim 14 , wherein a crossbar switch of the first cell is configured to receive, as input to the crossbar switch, output from a fourth cell.