Continuously variable dynamic element matching network
This disclosure relates to a system for mitigating distortion in a signal, including a plurality of bit-cells, a calculation circuit configured to determine a bit-cell population that is available to be activated for a given clock cycle, a dynamic element matching network configured to activate a subset of bit-cells of the bit-cell population, and a controller configured to control a pattern of activation of the subset of bit-cells of the bit-cell population.
1. A system for mitigating distortion in a signal comprising:
a plurality of bit-cells;
a calculation circuit configured to determine a bit-cell population that is available to be activated for a given clock cycle;
a dynamic element matching network configured to activate a subset of bit-cells of the bit-cell population; and
a controller configured to control a pattern of activation of the subset of bit-cells of the bit-cell population.
2. The system of claim 1 wherein the dynamic element matching network is further configured to activate each bit-cell of the subset of bit-cells on a first clock cycle, and deactivate each bit-cell of the subset of bit-cells on a second clock cycle.
3. The system of claim 2 wherein the second clock cycle is a clock cycle immediately following the first clock cycle.
4. The system of claim 2 wherein the dynamic element matching network is further configured to activate a second subset of bit-cells of the plurality of bit-cells on the second clock cycle, the second subset not including any bit-cells of the first subset.
5. The system of claim 1 , the calculation circuit being further configured to periodically determine the bit-cell population based on a peak signal strength of the signal.
6. The system of claim 5 wherein the calculation circuit determines the bit-cell population responsive to a signal strength of the signal being zero or near-zero.
7. The system of claim 1 wherein the subset of bit-cells is a second subset of bit-cells, and the dynamic element matching network further comprises a first shuffle network, a variable array, and a second shuffle network, wherein
the first shuffle network is configured to provide a first subset of bit-cells activated on a previous clock cycle to the variable array;
the variable array is configured to provide the bit-cells of the bit-cell population not including each bit-cell of the first subset of bit-cells to the second shuffle network, and to provide a number of bit-cells to be activated to the second shuffle network; and
the second shuffle network is configured to randomly select from among the bit-cell population not including the first subset of bit-cells the second subset of bit-cells to activate, the second subset of bit-cells including a number of bit-cells equal to the number of bit-cells to be activated.
8. The system of claim 7 wherein the first shuffle network is further configured to receive the second subset of bit-cells and provide the second subset to the variable array on a clock cycle following a clock cycle wherein the second subset of bit-cells was activated.
9. The system of claim 1 further comprising a barrel shifter, the barrel shifter being configured to activate the subset of bit-cells in a low population mode and the dynamic element matching network being configured to activate the subset of bit-cells in a high population mode.
10. The system of claim 9 wherein the system operates in the low population mode when the bit-cell population is below a threshold bit-cell population level.
11. A method of activating bit-cells of a plurality of bit-cells to mitigate distortion in a signal comprising:
determining a bit-cell population of the plurality of bit-cells to be available to be activated based on a signal strength of a signal;
randomly selecting a first subset of bit-cells of the bit-cell population to activate based on the signal strength;
activating the first subset of bit-cells on a first clock cycle; and
deactivating the first subset of bit-cells on a second clock cycle.
12. The method of claim 11 further comprising activating a second subset of bit-cells on the second clock cycle, the second subset not including any bit-cells of the first subset.
13. The method of claim 11 wherein the second clock cycle is the clock cycle immediately following the first clock cycle.
14. The method of claim 11 wherein the bit-cell population is determined at periodic intervals.
15. The method of claim 14 wherein the bit-cell population is determined when the signal strength of the signal is at or near zero.
16. The method of claim 11 wherein a bit-cell is activated for no more than one clock cycle in a row.
17. A dynamic element matching network (DEM) comprising:
an input;
a bit-cell population calculator coupled to the input;
a variable dynamic element matching network (variable DEM) coupled to the bit-cell population calculator and to a fixed-variable split calculator; and
an output coupled to the variable DEM.
18. The DEM network of claim 17 wherein the bit-cell population calculator is configured to determine a total number of bit-cells to be turned on during a clock cycle, the total number of bit-cells based on a signal strength of an input signal received at the input.
19. The DEM network of claim 18 wherein:
the variable DEM is configured to active a number of bit-cells equal to the total number of bit-cells.
20. The DEM network of claim 19 wherein:
the variable DEM is configured to deactivate the number of bit-cells on a clock cycle following a clock cycle on which the variable DEM activated the number of bit-cells.