IP Library Granted Patent US 12,272,656
Granted Patent B2
US 12,272,656 · App. 18/380,022 · Granted Apr 8, 2025

Heterogeneous nested interposer package for IC chips

Inventors: Debendra Mallik (Chandler, AZ); Ravindranath Mahajan (Chandler, AZ); Robert Sankman (Phoenix, AZ); Shawna Liff (Scottsdale, AZ); Srinivas Pietambaram (Chandler, AZ); Bharat Penmecha (Phoenix, AZ)
Assignee: Intel Corporation
H01L23/562H01L21/4853H01L21/4857H01L21/486H01L21/565H01L21/568H01L23/3128H01L23/5381H01L23/5384H01L23/5385H01L23/5386H01L24/16H01L2224/16227H01L2924/3511
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Quick Facts
Patent No.
US 12,272,656
App. No.
18/380,022
Granted
Apr 8, 2025
Kind
B2
Abstract

Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

Claims (46)

1. An electronics package, comprising:

a first mold layer;

a bridge embedded in the first mold layer, the bridge comprising through component vias;

a passive component embedded in the first mold layer, the passive component laterally spaced apart from the bridge;

a first die over a first portion of the bridge;

a second die over a second portion of the bridge and over the passive component, the second die laterally spaced apart from the first die, wherein the bridge electrically couples the first die and the second die, and wherein the second die is electrically coupled to the passive component;

a redistribution layer between the bridge and the first die and between the bridge and the second die; and

a second mold layer laterally between the first die and the second die.

2. The electronics package of claim 1 , wherein the passive component is a capacitor.

3. The electronics package of claim 1 , wherein the passive component is an inductor.

4. The electronics package of claim 1 , wherein the passive component is a resistor.

5. The electronics package of claim 1 , wherein the passive component is entirely within a footprint of the second die.

6. The electronics package of claim 1 , further comprising:

a second redistribution layer beneath the bridge.

7. The electronics package of claim 1 , further comprising:

a plurality of conductive balls beneath the bridge.

8. An electronics package, comprising:

an underfill material layer;

a first nested component embedded in the underfill material layer, the first nested component comprising through component vias;

a second nested component embedded in the underfill material layer, the second nested component laterally spaced apart from the first nested component;

a first die over a first portion of the first nested component;

a second die over a second portion of the first nested component and over the second nested component, the second die laterally spaced apart from the first die, wherein the first nested component electrically couples the first die and the second die, and wherein the second die is electrically coupled to the second nested component;

a redistribution layer between the first nested component and the first die and between the first nested component and the second die; and

a mold layer laterally between the first die and the second die.

9. The electronics package of claim 8 , wherein the second nested component is a capacitor.

10. The electronics package of claim 8 , wherein the second nested component is an inductor.

11. The electronics package of claim 8 , wherein the second nested component is a resistor.

12. The electronics package of claim 8 , wherein the second nested component is entirely within a footprint of the second die.

13. The electronics package of claim 8 , further comprising:

a second redistribution layer beneath the first nested component.

14. The electronics package of claim 8 , further comprising:

a plurality of conductive balls beneath the first nested component.

15. A method of fabricating an electronics package, the method comprising:

embedding a bridge embedded in a first mold layer, the bridge comprising through component vias;

embedding a passive component in the first mold layer, the passive component laterally spaced apart from the bridge;

providing a first die over a first portion of the bridge;

providing a second die over a second portion of the bridge and over the passive component, the second die laterally spaced apart from the first die, wherein the bridge electrically couples the first die and the second die, and wherein the second die is electrically coupled to the passive component;

forming a redistribution layer between the bridge and the first die and between the bridge and the second die; and

forming a second mold layer laterally between the first die and the second die.

16. The method of claim 15 , wherein the passive component is a capacitor.

17. The method of claim 15 , wherein the passive component is an inductor.

18. The method of claim 15 , wherein the passive component is a resistor.

19. The method of claim 15 , further comprising:

forming a second redistribution layer beneath the bridge.

20. The method of claim 15 , further comprising:

forming a plurality of conductive balls beneath the bridge.

Continuity (3)
Continuation 18089227 · Dec 27, 2022
Continuation 16437254 · Jun 11, 2019
Related Publication 20240038687A1 · Feb 1, 2024
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