Enhanced page information co-processor
A processing system includes a primary processor and a co-processor. The primary processor is couplable to a memory subsystem having at least one memory and operating to execute system software employing memory address translations based on one or more page tables stored in the memory subsystem. The co-processor is likewise couplable to the memory subsystem and operates to perform iterations of a page table walk through one or more page tables maintained for the memory subsystem and to perform one or more page management operations on behalf of the system software based the iterations of the page table walk. The page management operations performed by the co-processor include analytic data aggregation, free list management and page allocation, page migration management, page table error detection, and the like.
1 . A processing system, comprising:
a first processor including a translation lookaside buffer (TLB), the first processor configured to execute system software employing memory address translations based on one or more page tables stored in a memory subsystem; and
a second processor couplable to the memory subsystem, the second processor configured to perform iterations of a page table walk that checks each entry of one or more page tables maintained for the memory subsystem and to modify one or more existing TLB entries of the TLB based on the iterations of the page table walk.
2 . The processing system of claim 1 , wherein the second processor is configured to perform the iterations of the page table walk independent of a command from the first processor.
3 . The processing system of claim 1 , wherein the second processor is configured to maintain a free list of pages available for allocation based on the iterations of the page table walk.
4 . The processing system of claim 3 , wherein the second processor is configured to modify the one or more existing TLB entries based on the free list of pages available for allocation.
5 . The processing system of claim 3 , wherein the second processor is configured to:
based on allocating a page from the free list of pages available for allocation, update the TLB to include a TLB entry for the page.
6 . The processing system of claim 3 , wherein the second processor is configured to:
based on adding a page to the free list of pages available for allocation, invalidate an existing TLB entry associated with the page.
7 . The processing system of claim 1 , wherein the second processor is configured to:
make a modification to a page table entry of the one or more page tables based on the iterations of the page table walk; and
update an existing TLB entry of the one or more existing TLB entries based on the modification to the page table entry.
8 . A method, comprising:
executing, at a first processor including a translation lookaside buffer (TLB), system software employing memory address translations based on one or more page tables stored in a memory subsystem; and
performing, at a second processor coupled to the memory subsystem, iterations of a page table walk that checks each entry of one or more page tables maintained for the memory subsystem and to modify one or more existing TLB entries of the TLB based on the iterations of the page table walk.
9 . The method of claim 8 , wherein the second processor is configured to perform the iterations of the page table walk independent of a command from the first processor.
10 . The method of claim 8 , further comprising:
maintaining, at the second processor, a free list of pages available for allocation based on the iterations of the page table walk.
11 . The method of claim 10 , further comprising:
modifying the one or more existing TLB entries based on the free list of pages available for allocation.
12 . The method of claim 10 , further comprising:
based on allocating a page from the free list of pages available for allocation, updating, at the second processor, the TLB to include a TLB entry for the page.
13 . The method of claim 10 , further comprising:
based on adding a page to the free list of pages available for allocation, invalidating, at the second processor, an existing TLB entry associated with the page.
14 . The method of claim 8 , further comprising:
making a modification to a page table entry of the one or more page tables based on the iterations of the page table walk; and
updating, at the second processor, an existing TLB entry of the one or more existing TLB entries based on the modification to the page table entry.
15 . A processing system, comprising:
a first processor including a translation lookaside buffer (TLB), the first processor configured to execute system software employing memory address translations based on one or more page tables stored in a memory subsystem; and
a second processor couplable to the memory subsystem, the second processor configured to:
perform iterations of a page table walk through one or more page tables maintained for the memory subsystem;
maintain a free list of pages available for allocation based on the iterations of the page table walk; and
modify one or more existing TLB entries of the TLB based on the iterations of the page table walk.
16 . The processing system of claim 15 , wherein the second processor is configured to modify the one or more existing TLB entries based on the free list of pages available for allocation.
17 . The processing system of claim 16 , wherein the second processor is configured to:
update the TLB to include a TLB entry for the page based on allocating a page from the free list of pages available for allocation.
18 . The processing system of claim 16 , wherein the second processor is configured to:
invalidate an existing TLB entry associated with the page based on adding a page to the free list of pages available for allocation.
19 . The processing system of claim 16 , wherein the second processor is configured to:
make a modification to a page table entry of the one or more page tables based on the iterations of the page table walk; and
update an existing TLB entry of the one or more existing TLB entries based on the modification to the page table entry.
20 . The processing system of claim 16 , wherein the second processor is configured to perform the iterations of the page table walk independent of a command from the first processor.