High performance processor with improved microprogram execution triggered with a single issued execution trigger instruction
Implementations relate to a data processor that includes a data processing unit having a plurality of processing elements and a cache hierarchy including a plurality of levels of data caches. The data caches include a first level data cache connected to a second level data cache, and a main memory connected to the highest level cache of the cache hierarchy. At least one of the first level data cache or second level data cache is divided into a plurality of cache segments, and during operation of the data processor, at least some of the plurality of cache segments are excluded from cache operation. Each of the excluded cache segments is dedicated to an associated processing element as tightly coupled local access memory.
1 . A data processor implementing an instruction set architecture, the data processor comprising:
a plurality of processing elements;
a memory arrangement;
loading circuitry; and
an instruction issuer;
wherein, for each respective processing element of at least some of the processing elements:
the data processor is adapted for a part of the memory arrangement to be connected, at least temporarily, exclusively to the respective processing element;
the loading circuitry is adapted to initiate loading of a microprogram, which is formed of a sequence of codes that correspond to respective operations, from a memory hierarchy into the part of the memory arrangement that is connected, at least temporarily, exclusively to the respective processing element;
the respective processing element is adapted to respond to a single instruction received from the instruction issuer by executing an entirety of the microprogram using the connection of the respective processing element to the part of the memory arrangement that is connected, at least temporarily, to the respective processing element; and
the executing causes the respective processing element to produce a result data output by processing a received operand data.
2 . The data processor according to claim 1 , wherein the microprogram executed by the respective processing element forms a specific complex instruction.
3 . The data processor according to claim 2 , wherein an opcode in an assembly program issued to the respective processing element references the microprogram.
4 . The data processor according to claim 1 , wherein the microprogram executed by the respective processing element appears to a program outside of the microprogram as a single complex instruction.
5 . The data processor according to claim 4 , wherein the microprogram executed by the respective processing element forms a specific complex instruction, and wherein an opcode in an assembly program issued to the respective processing element references the microprogram.
6 . The data processor according to claim 1 , wherein the part of the memory arrangement is part of a cache memory within a cache hierarchy, and is available for transferring data with at least one load unit and at least one store unit.
7 . The data processor according to claim 6 , wherein the part of the memory arrangement is selectively switchable between use as microprogram memory and as a cache.
8 . The data processor according to claim 6 , wherein the part of the memory arrangement is selectively switchable between use as microprogram memory, as a cache, and as tightly coupled memory.
9 . The data processor according to claim 1 , wherein the part of the memory arrangement is used to store data to which the respective processing element has at least one of read and write access during the execution of the microprogram.
10 . The data processor according to claim 1 , wherein the sequence of codes of the microprogram are a plurality of microcode instructions.
11 . The data processor according to claim 10 , wherein the microcode instructions have access to a register file formed of registers dedicated and local to the respective processing element.
12 . The data processor according to claim 10 , wherein the microcode instructions have access to a processing element operand data input register.
13 . The data processor according to claim 10 , wherein the microcode instructions have access to a processing element result data output register.
14 . The data processor according to claim 10 , wherein the microcode instructions include jump instructions for jumping to a target address.
15 . The data processor according to claim 10 , wherein the microcode instructions include conditional jump instructions for jumping to a target address depending on a condition.
16 . The data processor according to claim 10 , wherein the microcode instructions include loop instructions to form program loops.
17 . The data processor according to claim 1 , wherein the single instruction is a microprogram call instruction that indicates an address of a start of the microprogram within the part of the memory arrangement.
18 . The data processor according to claim 1 , wherein the microprogram comprises conditional instructions, allowing for the execution to branch based on data values or status flags.
19 . The data processor according to claim 1 , wherein the microprogram comprises instructions whose execution includes modification of an address pointer, allowing for sequential access to data within the part of the memory arrangement.
20 . The data processor according to claim 1 , wherein the microprogram defines actions whose execution spans a plurality of clock cycles.