IP Library Granted Patent US 12,640,210
Granted Patent B2
US 12,640,210 · App. 18/384,927 · Granted May 26, 2026

Serial interface receiver and an offset calibration method thereof

Inventors: Dam Yun (Suwon-si, KR); Dongyeon Kwag (Suwon-si, KR); Dongwoo Baek (Suwon-si, KR); Jehyung Yoon (Suwon-si, KR); Sangik Cho (Suwon-si, KR); Dae-Hoon Han (Suwon-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
G11C16/30H03F3/45475H03K17/56
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Quick Facts
Patent No.
US 12,640,210
App. No.
18/384,927
Granted
May 26, 2026
Kind
B2
Abstract

A parallel e-fuse device including: a first e-fuse to receive an input voltage and transfer a first fuse current to an output terminal; and a second e-fuse to receive the input voltage and transfer a second fuse current to the output terminal, the first e-fuse includes: a power transistor to control the first fuse current according to a gate voltage; a clamp amplifier to provide a charging current to charge a gate of the power transistor, the charging current being obtained by monitoring a feedback voltage; a balance amplifier to provide a first sinking current to discharge the gate of the power transistor, the first sinking current being obtained by comparing a current sensing signal with a current monitoring signal, wherein the clamp amplifier generates the charging current according to a differential voltage between the feedback voltage and a reference voltage.

Claims (15)

1 . A parallel e-fuse device comprising:

a first e-fuse configured to receive an input voltage and transfer a first fuse current to an output terminal, and

a second e-fuse configured to receive the input voltage and transfer a second fuse current to the output terminal,

wherein the first e-fuse comprises:

a power transistor configured to control a magnitude of the first fuse current according to a gate voltage and transmit the first fuse current to the output terminal;

a clamp amplifier configured to provide a charging current to charge a gate of the power transistor, the charging current being obtained by monitoring a feedback voltage obtained by feeding back a voltage of the output terminal;

a balance amplifier configured to provide a first sinking current to discharge the gate of the power transistor, the first sinking current being obtained by comparing a current sensing signal obtained by sensing the first fuse current with a current monitoring signal that corresponds to a result of monitoring the second fuse current,

wherein the clamp amplifier generates the charging current according to a differential voltage between the feedback voltage and a reference voltage.

2 . The device of claim 1 , wherein the clamp amplifier generates the charging current smaller than the first sinking current when the differential voltage is ‘0V’ or less.

3 . The device of claim 1 , wherein when a difference between the feedback voltage and the reference voltage is equal to or less than a reference value, the parallel e-fuse device operates in a soft-start mode or a clamping mode.

4 . The device of claim 1 , wherein the clamp amplifier generates the charging current greater than the first sinking current when the differential voltage is greater than a reference value.

5 . The device of claim 1 , wherein the first e-fuse includes an active current mirror for mirroring the charging current to the gate of the power transistor using a charge pump voltage.

6 . The device of claim 1 , wherein the first e-fuse includes a mode detection amplifier configured to generate the reference voltage using a clamp reference voltage and a ramp voltage.

7 . The device of claim 1 , wherein the first e-fuse includes a current sensor configured to sense the first fuse current and generate the current sensing signal.

8 . The device of claim 7 , wherein the first e-fuse includes an overcurrent protection amplifier configured to generate a second sinking current to discharge the gate of the power transistor, the second sinking current being obtained by comparing the current sensing signal with an overcurrent reference level.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 30, 2023
From: YUN, DAM; KWAG, DONGYEON; BAEK, DONGWOO; YOON, JEHYUNG; CHO, SANGIK; HAN, DAE-HOON
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 065388/0219 →
Priority Claims (1)
KR 10-2023-0049193 · Apr 14, 2023 · national
Continuity (1)
Related Publication 20240347114A1 · Oct 17, 2024
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