Implementing Efuse sense amplifier testing without blowing the Efuse
View Patent ↗A method and apparatus implement effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse, and a design structure on which the subject circuit resides is provided. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.
1. A design structure tangibly embodied in a computer-readable storage medium for designing, manufacturing, or testing a design, the design structure comprising:
a testing circuit tangibly embodied in the computer-readable storage medium used in the design process, said testing circuit for testing a sense amplifier for an eFuse to determine whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse; said testing circuit including
a sense amplifier signal control providing a first precharge signal applied to a first precharge device of the sense amplifier;
said sense amplifier signal control providing a second precharge signal applied to a second precharge device of the sense amplifier; and
said sense amplifier signal control selectively controlling said first and second precharge devices for providing a respective output resulting from both an unblown and a blown eFuse of the sense amplifier with the eFuse being unblown, wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said testing circuit.
2. The design structure of claim 1 , wherein the design structure comprises a netlist, which describes said testing circuit.
3. The design structure of claim 1 , wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.
4. The design structure of claim 1 , wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.
5. The design structure of claim 1 , wherein said first precharge device and said second precharge device respectively precharge a true sense node and a complement sense node of the sense amplifier to a high voltage during normal operation.
6. The design structure of claim 5 , wherein said sense amplifier signal control selectively controlling said precharge devices includes said sense amplifier signal control selectively controlling said precharge devices for providing a “0” and “1” output of the sense amplifier with the eFuse being unblown.
7. The design structure of claim 5 , wherein said sense amplifier signal control selectively controlling said precharge devices includes said sense amplifier signal control applying sensing control signals to a first control transistor coupled to said first precharge device and a second control transistor coupled to said second precharge device.
8. The design structure of claim 7 , wherein the sense amplifier includes a cross-coupled inverter circuit coupled between said true sense node and said complement sense node of the sense amplifier, a first pull-up transistor coupled between said cross-coupled inverter circuit and a voltage supply rail, and a second pull-down transistor coupled to between said cross-coupled inverter circuit and a ground potential; and wherein said sense amplifier signal control selectively controlling said precharge devices includes said sense amplifier signal control applying sensing control signals to said first pull-up transistor and said second pull-down transistor.
9. The design structure of claim 8 , wherein said pull-up transistor includes a P-channel field effect transistor and said pull-down transistor includes an N-channel field effect transistor.
10. The design structure of claim 5 , wherein said first precharge device and said second precharge device include a respective P-channel field effect transistor.
11. The design structure of claim 5 , wherein the eFuse coupled to said true sense node.
12. The design structure of claim 5 includes a reference resistor coupled to said complement sense node.