Granted Patent B2

US 12,660,364 · App. 18/386,544 · Granted Jun 16, 2026

Inventors: Chengfa Liu (Changzhou, CN); Hong Chen (Changzhou, CN); Daming Chen (Changzhou, CN); Yifeng Chen (Changzhou, CN)

Assignee: TRINA SOLAR CO., LTD.

H10F71/129H10F71/00H10F71/121H10F77/211H10F77/703H10F77/311

Abstract

Claims (31)

1 . A method for manufacturing a solar cell, comprising:

providing a wafer, wherein the wafer comprises a substrate and a doped conducting material layer, the substrate comprises a first surface, a second surface, and a plurality of first side surfaces, the first surface and the second surface are opposite to each other, the plurality of first side surfaces are adjacent to and between the first surface and the second surface, the first surface and a portion of the first side surface of the substrate comprise a textured structure, the doped conducting material layer is disposed on the first surface and the portion of the first side surface to cover the textured structure;

forming a passivating contact material layer on each surface of the wafer;

cutting the wafer formed with the passivating contact material layer along the thickness direction of the substrate to form a sub-wafer, so as to cut the doped conducting material layer into a doped conducting layer;

etching to remove the passivating contact material layer on a surface of a first side of the sub-wafer and on each side surface of the sub-wafer, thereby forming a passivating contact layer on the sub-wafer, wherein the surface of the first side of the sub-wafer corresponds to the first surface of the substrate; and

forming a first passivation layer on the doped conducting layer, wherein the first passivation layer covers the first surface and at least the portion of the first side surface, so as to cover at least the doped conducting layer, and the first passivation layer further covers at least a portion of a cut edge side surface, the cut edge side surface is a side surface of the sub-wafer formed by cutting the wafer.

2 . The method according to claim 1 , wherein the providing the wafer comprises:

performing texturing treatment and diffusion of dopant elements to at least the first surface and the first side surface of the substrate; and

etching the substrate to expose the second surface and a first target region of each first side surface of the substrate;

wherein the first target region is adjacent to and connected to the second surface.

3 . The method according to claim 2 , wherein the etching the substrate to expose the second surface and the first target region of each first side surface of the substrate comprises:

etching the substrate subjected to the texture treatment and the diffusion of dopant elements to expose the texture structure in the second surface and the first target region; and

etching to remove the exposed textured structure, so as to expose the second surface and the first target region of each first side surface of the substrate.

4 . The method according to claim 1 , wherein the forming the passivating contact material layer on each surface of the wafer comprises:

sequentially forming a tunnel material layer, a doped polysilicon material layer, and an oxide material layer on each surface of the wafer.

5 . The method according to claim 4 , wherein the etching to remove the passivating contact material layer on the surface of the first side of the sub-wafer and on each side surface of the sub-wafer to form the passivating contact layer on the sub-wafer comprises:

etching to remove the oxide material layer on the surface of the first side of the sub-wafer and on each side surface of the sub-wafer,

etching to remove the doped polysilicon material layer and the tunnel material layer on the surface of the first side of the sub-wafer and on each side surface of the sub-wafer; and

etching to polish the cut edge side surface of the sub-wafer.

6 . The method according to claim 5 , wherein the etching to remove the oxide material layer is performed by using a continuous-type machine; and the etching to remove the doped polysilicon material layer and the tunnel material layer is performed by using a trough-type machine.

7 . The method according to claim 5 , wherein after the etching to remove the doped polysilicon material layer and the tunnel material layer on the surface of the first side of the sub-wafer and on each side surface of the sub-wafer, the method further comprises:

etching to remove the oxide material layer on a surface of a second side of the sub-wafer;

wherein the surface of the second side of the sub-wafer corresponds to the second surface of the substrate.

8 . The method according to claim 1 , wherein after the forming the first passivation layer on the doped conducting layer, the method further comprises:

forming a second passivation layer on the passivating contact layer;

wherein the second passivation layer at least covers the second surface, at least a portion of the first side surface, and at least a portion of the cut edge side surface, so as to cover the passivating contact layer and at least a portion of the first passivation layer.

9 . The method according to claim 8 , wherein after the forming the second passivation layer on the passivating contact layer, the method further comprises:

respectively forming electrodes on the first passivation layer and the second passivation layer.

10 . The method according to claim 9 , wherein the electrodes are formed such that one of the electrodes located at one side of the substrate penetrates the first passivation layer and is electrically connected to the doped conducting layer, and another of the electrodes located at another side of the substrate penetrates the second passivation layer and is electrically connected to the passivating contact layer.

11 . The method according to claim 1 , wherein the cutting the wafer formed with the passivating contact material layer along the thickness direction of the substrate to form the sub-wafers comprises:

laser cutting the wafer formed with the passivating contact material layer along the thickness direction of the substrate to form the sub-wafer.

Assignments (2)

Priority Claims (1)

Continuity (1)

References Cited (54)