IP Library Granted Patent US 12,119,820
Granted Patent B2
US 12,119,820 · App. 18/387,402 · Granted Oct 15, 2024

Superconducting field-programmable gate array

Inventors: Faraz Najafi (Palo Alto, CA); Qiaodan Jin Stone (Sunnyvale, CA)
Assignee: PSIQUANTUM CORP.
H03K19/195G01J1/44H10N60/30H10N60/84G01J2001/442
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Quick Facts
Patent No.
US 12,119,820
App. No.
18/387,402
Granted
Oct 15, 2024
Kind
B2
Abstract

A programmable circuit includes a superconducting multi-dimensional array. The programmable circuit further includes a plurality of photon detectors coupled to respective portions of the superconducting multi-dimensional array, each photon detector configured to selectively provide input to a corresponding respective portion sufficient to transition the corresponding respective portion from a superconducting state to a non-superconducting state. The programmable circuit also includes one or more electrical terminals coupled to respective second portions of the superconducting multi-dimensional array.

Claims (22)

1. A programmable circuit, comprising:

a superconducting multi-dimensional array;

a plurality of photon detectors coupled to respective portions of the superconducting multi-dimensional array, each photon detector configured to selectively provide input to a corresponding respective portion sufficient to transition the corresponding respective portion from a superconducting state to a non-superconducting state; and

one or more electrical terminals coupled to respective second portions of the superconducting multi-dimensional array.

2. The programmable circuit of claim 1 , wherein in a first configuration, the superconducting multi-dimensional array is configured to perform a logical operation.

3. The programmable circuit of claim 2 , wherein in a second configuration, the superconducting multi-dimensional array is configured to perform an additional logical operation that is different from the logical operation of the first configuration.

4. The programmable circuit of claim 3 , wherein the logical operation comprises one or more of: a logical AND operation; a logical OR operation; a majority gate operation; and an input counting operation.

5. The programmable circuit of claim 1 , wherein the superconducting multi-dimensional array is a two-dimensional array.

6. The programmable circuit of claim 1 , wherein the superconducting multi-dimensional array is patterned from a single thin film of superconducting material.

7. The programmable circuit of claim 1 , further comprising a current source coupled to the superconducting multi-dimensional array, the current source configured to provide a current to the superconducting multi-dimensional array.

8. The programmable circuit of claim 7 , wherein the current is adapted to maintain the superconducting multi-dimensional array in a superconducting state in the absence of a signal from the plurality of photon detectors.

9. The programmable circuit of claim 7 , wherein the current source is further configured to reset the superconducting multi-dimensional array after the superconducting multi-dimensional array transitions to a non-superconducting state.

10. The programmable circuit of claim 1 , wherein the plurality of photon detectors is electrically isolated from the superconducting multi-dimensional array.

11. The programmable circuit of claim 10 , wherein the plurality of photon detectors are positioned adjacent to the respective portions of the superconducting multi-dimensional array.

12. The programmable circuit of claim 1 , further comprising a readout circuit coupled to one of the one or more electrical terminals.

13. The programmable circuit of claim 1 , further comprising a plurality of input components coupled to respective third portions of the superconducting multi-dimensional array, the plurality of input components configured to maintain the respective third portions in one or more steady states.

14. The programmable circuit of claim 13 , wherein the plurality of input components comprise a plurality of semiconductor components.

15. The programmable circuit of claim 1 , further comprising one or more reference nodes coupled to the one or more electrical terminals.

16. The programmable circuit of claim 1 , wherein the respective portions of the superconducting multi-dimensional array each have a width ranging from 50 nanometers to 5 microns.

17. The programmable circuit of claim 1 , wherein the respective portions of the superconducting multi-dimensional array each have a length ranging from 200 nanometers to 2 microns.

18. The programmable circuit of claim 1 , wherein the superconducting multi-dimensional array includes a first number of columns and a second number of rows, wherein the first number is different than the second number.

19. The programmable circuit of claim 1 , wherein a first set of columns of the superconducting multi-dimensional array have a first number of rows, and a second set of columns of the superconducting multi-dimensional array have a second number of rows, different from the first number.

Continuity (8)
Continuation 17838917 · Jun 13, 2022
Continuation 17135861 · Dec 28, 2020
Continuation 16473550 · Jun 25, 2019
Continuation PCTUS2019017691 · Feb 12, 2019
Provisional Application 62660192 · Apr 19, 2018
Provisional Application 62632323 · Feb 19, 2018
Provisional Application 62630657 · Feb 14, 2018
Related Publication 20240080029A1 · Mar 7, 2024
Cited By (1)
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