IP Library Granted Patent US 12,164,795
Granted Patent B2
US 12,164,795 · App. 18/390,844 · Granted Dec 10, 2024

Inter-memory movement in a multi-memory system

Inventors: Sourabh Dhir (Boise, ID); Kang-Yong Kim (Boise, ID)
Assignee: Micron Technology, Inc.
G06F3/0647G06F3/0616G06F3/0635G06F3/0653G06F3/0659G06F3/0683
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Quick Facts
Patent No.
US 12,164,795
App. No.
18/390,844
Granted
Dec 10, 2024
Kind
B2
Abstract

Methods, systems, and devices for improved inter-memory movement in a multi-memory system are described. A memory device may receive from a host device a command to move data from a first memory controlled by a first controller to a second memory controller by a second controller. The memory device may use the first and second controllers to facilitate the movement of the data from the first memory to the second memory via a path external to the host device. The memory device may indicate to the host device when to suspend activity to the first memory or the second memory and when to resume activity to the first memory or second memory.

Claims (51)

1. An apparatus, comprising:

a first controller for a first memory;

a second controller for a second memory; and

one or more controllers coupled with the first memory and the second memory, the one or more controllers configured to cause the apparatus to:

receive, from a host device, a command to move data;

determine, based on the command being an inter-memory data movement command for data movement between the first memory and the second memory via a data path external to the host device, that a direction of the data movement is from the first memory to the second memory;

transmit, to the host device from the first controller, an indication for the host device to suspend access activity to the second memory based on the command being an inter-memory data movement command, wherein the indication to suspend access activity is transmitted after transmission, to the second controller, of a read command for the data based on the direction of data movement being from the first memory to the second memory; and

transmit, based on transmitting the read command, the data from the first memory to the second memory via the data path external to the host device.

2. The apparatus of claim 1 , wherein the second memory has a deterministic access timing and the first memory has a non-deterministic access timing, and wherein the indication to suspend access activity is transmitted after transmission of the read command based on the first memory having the non-deterministic access timing.

3. The apparatus of claim 1 , wherein the one or more controllers are further configured to cause the apparatus to:

determine that the data is ready for transmission from the first memory to the second memory, wherein the indication to suspend access activity is transmitted based on determining that the data is ready for transmission.

4. The apparatus of claim 1 , wherein the one or more controllers are further configured to cause the apparatus to:

determine that the command is associated with multiple memories of the apparatus, wherein the command is determined to be an inter-memory data movement command based on determining that the command is associated with the multiple memories.

5. The apparatus of claim 1 , wherein the one or more controllers are further configured to cause the apparatus to:

transmit, by the first controller, an indication for the host device to resume activity to the second memory based on determining that the data has been transmitted from the first memory to the second memory.

6. The apparatus of claim 1 , wherein the command is associated with a first address of the first memory, and wherein the one or more controllers are further configured to cause the apparatus to:

transmit an indication of the first address from the first controller to the first memory, wherein the indication to suspend access activity is transmitted after transmission of the indication of the first address based on the direction of data movement being from the first memory to the second memory.

7. The apparatus of claim 6 , wherein the command is associated with a second address of the second memory, and wherein the one or more controllers are further configured to cause the apparatus to:

transmit an indication of the second address from the first controller to the second controller, wherein the indication to suspend access activity is transmitted before transmission of the second address based on the direction of data movement being from the first memory to the second memory.

8. A method, comprising:

receiving, at an apparatus comprising a first memory and a second memory, a command to move data;

determining, based on the command being an inter-memory data movement command for data movement between the first memory and the second memory via a data path external to a host device, that a direction of the data movement is from the first memory to the second memory;

transmit, to a host device from a first controller for the first memory, an indication for the host device to suspend access activity to the second memory based on the command being an inter-memory data movement command, wherein the indication to suspend access activity is transmitted after transmission of a read command, to a second controller for the second memory, for the data based on the direction of data movement being from the first memory to the second memory; and

transmit, based on transmitting the read command, the data from the first memory to the second memory via the data path external to the host device.

9. The method of claim 8 , wherein the second memory has a deterministic access timing and the first memory has a non-deterministic access timing, and wherein the indication to suspend access activity is transmitted after transmission of the read command based on the first memory having the non-deterministic access timing.

10. The method of claim 8 , further comprising:

determining that the data is ready for transmission from the first memory to the second memory, wherein the indication to suspend access activity is transmitted based on determining that the data is ready for transmission.

11. The method of claim 8 , further comprising:

determining that the command is associated with multiple memories of the apparatus, wherein the command is determined to be an inter-memory data movement command based on determining that the command is associated with multiple memories.

12. The method of claim 8 , wherein the command is associated with a first address for the first memory and a second address for the second memory.

13. The method of claim 12 , further comprising:

transmitting, by the first controller for the first memory, the first address to the first memory and before transmitting the indication to suspend access activity; and

transmitting, by the first controller, the second address to the second controller for the second memory after transmitting the indication to suspend access activity.

14. The method of claim 8 , further comprising:

transmitting an indication for the host device to resume activity to the second memory based on determining that the data has been transmitted from the second memory to the first memory.

15. An apparatus, comprising:

a first controller for a first memory;

a second controller for a second memory; and

one or more controllers coupled with the first memory and the second memory, the one or more controllers configured to cause the apparatus to:

determine, based on a received command being an inter-memory data movement command for data movement between the first memory and the second memory, that a direction of the data movement is from the second memory to the first memory;

transmit, to a host device from the first controller, an indication that the host device is to suspend access activity to the second memory based on the command being an inter-memory data movement command, wherein the indication to suspend access activity is transmitted before transmission of a read command, to the second controller, for the data based on the direction of data movement being from the second memory to the first memory; and

transmit, based on transmitting the indication of the read command, the data from the second memory to the first memory via a data path external to the host device.

16. The apparatus of claim 15 , wherein the second memory has a deterministic access timing and the first memory has a non-deterministic access timing, and wherein the indication to suspend access activity is transmitted before transmission of the read command based on the first memory having the non-deterministic access timing.

17. The apparatus of claim 15 , wherein the one or more controllers are further configured to cause the apparatus to:

determine that the command is associated with multiple memories of the apparatus, wherein the command is determined to be an inter-memory data movement command based on determining that the command is associated with multiple memories.

18. The apparatus of claim 15 , wherein the command is associated with a first address for the first memory and a second address for the second memory, and wherein the one or more controllers are further configured to cause the apparatus to:

transmit, by the first controller, an indication of the second address to the second controller after transmitting the indication to suspend access activity.

19. The apparatus of claim 18 , wherein the one or more controllers are further configured to cause the apparatus to:

transmit, by the first controller, an indication of the first address to the first memory based on transmitting the indication of the second address to the second controller.

20. The apparatus of claim 15 , wherein the one or more controllers are further configured to cause the apparatus to:

transmit, by the first controller, an indication for the host device to resume activity to the second memory based on determining that the data has been transmitted from the second memory to the first memory.

Continuity (3)
Continuation 17018570 · Sep 11, 2020
Provisional Application 63072604 · Aug 31, 2020
Related Publication 20240201885A1 · Jun 20, 2024