Processor-guided execution of offloaded instructions using fixed function operations
Processor-guided execution of offloaded instructions using fixed function operations is disclosed. Instructions designated for remote execution by a target device are received by a processor. Each instruction includes, as an operand, a target register in the target device. The target register may be an architected virtual register. For each of the plurality of instructions, the processor transmits an offload request in the order that the instructions are received. The offload request includes the instruction designated for remote execution. The target device may be, for example, a processing-in-memory device or an accelerator coupled to a memory.
1. A processor comprising:
at least one processor core;
at least one memory controller configured for communication with a processing-in-memory (PIM) device of a memory device, wherein the processor is configured to:
write data identifying a set of operations to a command buffer of the PIM device; and
transmit one or more offload requests generated in response to one or more offload instructions, wherein the one or more offload requests direct the PIM device to execute the set of operations in the command buffer.
2. The processor of claim 1 , wherein an offload request indicates an entry in the command buffer that includes an operation for execution by the PIM device.
3. The processor of claim 1 , wherein the data identifying the set of operations is written to the command buffer of the PIM device upon launching a thread on the processor core.
4. The processor of claim 1 , wherein a first offload instruction of the one or more offload instructions is associated with metadata that includes a pointer to an entry in the command buffer.
5. The processor of claim 1 , wherein each instruction of the one or more offload instructions includes, as an operand, a target register in the PIM device; and wherein the processor implements an instruction set architecture extension that identifies the target register as a virtual register.
6. The processor of claim 1 , wherein each of the one or more offload instructions includes an opcode from a group of opcodes in an instruction set architecture extension implemented by the processor; and wherein the group of opcodes in the instruction set architecture extension includes a remote load opcode, a remote computation opcode, and a remote store opcode.
7. The processor of claim 1 , wherein to transmit the one or more offload requests generated in response to the one or more offload instructions the processor is further configured to:
generate a memory address for an offload instruction; and
couple the memory address with the offload request.
8. The processor of claim 1 , wherein to transmit the one or more offload requests generated in response to the one or more offload instructions the processor is further configured to:
obtain local data for the offload instruction; and
couple the local data with the offload request.
9. The processor of claim 1 , wherein to transmit the one or more offload requests generated in response to the one or more offload instructions the processor is further configured to:
buffer the offload requests until after an oldest instruction in the one or more offload instructions has retired; and
transmit, for each of the one or more instructions in an order received, an offload request.
10. The processor of claim 1 , wherein the processor is further configured to perform a cache operation on one or more caches that contain an entry corresponding to a memory address included in the offload request, wherein the cache operation includes at least one of invalidating a cache entry containing clean data and flushing a cache entry containing dirty data.
11. The processor of claim 10 , wherein the cache operation is performed on a plurality of caches that contain an entry corresponding to a memory address included in the offload request, and wherein the plurality of caches is distributed across a plurality of core clusters each including a plurality of processor cores.
12. A system comprising:
a processing-in-memory (PIM) device; and
a processor coupled to the PIM device, the processor configured to:
write data identifying a set of operations to a command buffer of the PIM device; and
transmit one or more offload requests generated in response to one or more offload instructions, wherein the one or more offload requests direct the PIM device to execute the set of operations in the command buffer.
13. The system of claim 12 , wherein an offload request indicates an entry in the command buffer that includes an operation for execution by the PIM device.
14. The system of claim 12 , wherein each instruction of the one or more offload instructions includes, as an operand, a target register in the PIM device; and wherein the processor implements an instruction set architecture extension that identifies the target register as a virtual register.
15. The system of claim 12 , wherein to transmit the one or more offload requests generated in response to the one or more offload instructions the processor is further configured to:
generate a memory address for an offload instruction; and
couple the memory address with the offload request.
16. The system of claim 12 , wherein to transmit the one or more offload requests generated in response to the one or more offload instructions the processor is further configured to:
obtain local data for the offload instruction; and
couple the local data with the offload request.
17. The system of claim 12 , wherein to transmit one or more offload requests generated in response to one or more offload instructions the processor is further configured to:
buffer the offload requests until after an oldest instruction in the one or more offload instructions has retired; and
transmit, for each of the one or more offload instructions in an order received, an offload request.
18. The system of claim 12 , wherein the processor is further configured to perform a cache operation on one or more caches that contain an entry corresponding to a memory address included in the offload request, wherein the cache operation includes at least one of invalidating a cache entry containing clean data and flushing a cache entry containing dirty data.
19. A method of processor-guided execution of offloaded instructions using fixed function operations, the method comprising:
writing data identifying a set of operations to a command buffer of a processing-in-memory (PIM device); and
transmitting one or more offload requests generated in response to one or more offload instructions, wherein the one or more offload requests direct the PIM device to execute the set of operations in the command buffer.
20. The method of claim 19 , wherein an offload request indicates an entry in the command buffer that includes an operation for execution by the PIM device.