IP Library › Granted Patent US 12,277,891
Granted Patent B2
US 12,277,891 · App. 18/395,068 · Granted Apr 15, 2025

Display apparatus and driving method thereof

Inventor: Jaesik Hwang (Gunpo-si, KR)
Assignee: LG Display Co., Ltd.
G09G3/2096G09G3/3233H10K59/131G09G2300/0426G09G2300/0819G09G2300/0842G09G2300/0861G09G2310/08G09G2320/046G09G2330/021
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,277,891
App. No.
18/395,068
Granted
Apr 15, 2025
Kind
B2
Abstract

The present disclosure relates to a display apparatus and a diving method thereof that can prevent a dark spot caused by a leakage of a reset voltage to the anode electrode of a light emitting diode. In the display apparatus, a first (anode) electrode of a light emitting diode EL, one electrode (a source or drain electrode) of an emission transistor T 4 , and one electrode (a source or drain electrode) of a reset transistor T 6 connect to one another, and a fourth gate electrode of the emission transistor T 4 and a sixth gate electrode of the reset transistor T 6 connect to an emission control signal line EML, solving the problem of a dark spot, ensuring improvement in the quality and reliability of a product, and enabling a narrow bezel.

Claims (65)

1. A display apparatus, comprising:

a light emitting element comprising a first electrode and a second electrode;

an emission transistor comprising a first electrode of the emission transistor, a second electrode of the emission transistor that is connected to the first electrode of the light emitting element, and a fourth gate electrode; and

a reset transistor comprising a first electrode of the reset transistor that is connected to the first electrode of the light emitting element, a second electrode of the reset transistor that is connected to a reset voltage line, and a sixth gate electrode that is connected to the fourth gate electrode,

wherein the second electrode of the light emitting element is connected to a second power source line, and the fourth gate electrode and the sixth gate electrode are respectively connected to an emission control signal line.

2. The display apparatus of claim 1 , wherein the first electrode of the light emitting element comprises an anode electrode.

3. The display apparatus of claim 1 , wherein the second electrode of the light emitting element comprises a cathode electrode.

4. The display apparatus of claim 1 , wherein in the emission transistor, the first electrode of the emission transistor is a source electrode and the second electrode of the emission transistor is a drain electrode, or the first electrode of the emission transistor is a drain electrode and the second electrode of the emission transistor is a source electrode.

5. The display apparatus of claim 1 , wherein in the reset transistor, the first electrode of the reset transistor is a source electrode and the second electrode of the reset transistor is a drain electrode, or the first electrode of the reset transistor is a drain electrode and the second electrode of the reset transistor is a source electrode.

6. The display apparatus of claim 1 , wherein the light emitting element comprises an organic electric field light emitting diode.

7. The display apparatus of claim 1 , wherein the emission transistor is a P-type thin film transistor.

8. The display apparatus of claim 1 , wherein the reset transistor is an N-type thin film transistor.

9. The display apparatus of claim 1 , wherein the emission transistor is a low-temperature polycrystalline silicon (LTPS) thin film transistor.

10. The display apparatus of claim 1 , wherein the reset transistor is an oxide thin film transistor.

11. A display apparatus, comprising:

a display panel comprising a plurality of pixels;

an emission driver configured to provide an emission control signal to each of the plurality of pixels;

a scan driver configured to provide a scan signal to each of the plurality of pixels;

a data driver configured to provide a data voltage to each of the plurality of pixels; and

a controller configured to control the scan driver, the data driver, and the emission driver,

wherein each of the plurality of pixels comprises:

a light emitting element comprising a first electrode connected to a fifth node, and a second electrode connected to a low-potential driving voltage;

a fourth transistor comprising a first electrode of the fourth transistor that is connected to a third node, a second electrode of the fourth transistor that is connected to the fifth node, and a fourth gate electrode that is connected to node A of an emission control signal line; and

a sixth transistor comprising a first electrode of the sixth transistor that is connected to a reset voltage line, a second electrode of the sixth transistor that is connected to the fifth node, and a sixth gate electrode that is connected to the node A.

12. The display apparatus of claim 11 , further comprising:

a driving transistor comprising a first electrode of the driving transistor that is connected to a second node, a second electrode of the driving transistor that is connected to the third node, and a gate electrode connected to a first node;

a first transistor comprising a first electrode of the first transistor that is connected to the first node, a second electrode of the first transistor that is connected to the third node, and a first gate electrode that receives a first scan signal;

a second transistor comprising a first electrode of the second transistor that receives the data voltage, a second electrode of the second transistor that is connected to the second node, and a second gate electrode that receives a second scan signal;

a third transistor comprising a first electrode of the third transistor that is connected to a fourth node and receives a high-potential diving voltage, a second electrode of the third transistor that is connected to the second node, and a third gate electrode that receives the emission control signal;

a fifth transistor comprising a first electrode of the fifth transistor that receives a bias voltage, a second electrode of the fifth transistor that is connected to the second node, and a fifth gate electrode that receives a third scan signal;

a seventh transistor comprising a first electrode of the seventh transistor that receives a second initialization voltage, a second electrode of the seventh transistor that is connected to the first node, and a gate electrode of the seventh transistor that receives a fourth scan signal; and

a storage capacitor connecting the first node and the fourth node.

13. A display apparatus, comprising:

a substrate comprising a display area and a non-display area;

a buffer layer on the substrate;

a first insulation layer on the buffer layer;

a fourth semiconductor layer of an emission transistor and a sixth semiconductor layer of a reset transistor on the first insulation layer;

a second insulation layer on the first insulation layer, the fourth semiconductor layer, and the sixth semiconductor layer;

a low-potential driving power source line, a fourth gate electrode of the emission transistor, and a sixth gate electrode of the reset transistor on the second insulation layer;

a third insulation layer on the second insulation layer, the low-potential driving power source line, the fourth gate electrode, and the sixth gate electrode;

a first electrode and a second electrode of the emission transistor on the third insulation layer and contacting the fourth semiconductor layer through a first contact hole, and a first electrode and a second electrode of the reset transistor on the third insulation layer and contacting the sixth semiconductor layer through a second contact hole;

a protective layer on the third insulation layer, the first electrode and the second electrode of the emission transistor, and the first electrode and the second electrode of the reset transistor;

a first intermediate layer on the protective layer in the display area;

a connection electrode on the first intermediate layer in the display area, and contacting the first electrode or the second electrode of the emission transistor through a third contact hole and contacting the first electrode or the second electrode of the reset transistor;

a second intermediate layer on the first intermediate layer and the connection electrode in the display area;

a first electrode of a light emitting element on the second intermediate layer in the display area, and contacting the connection electrode through a fourth contact hole;

a bank layer on the second intermediate layer, except for the first electrode of the light emitting element in the display area;

an emission layer on the bank layer and the first electrode of the light emitting element in the display area;

a second electrode of the light emitting element on the emission layer in the display area; and

an encapsulation layer on the second electrode of the light emitting element in the display area, and on the protective layer in the non-display area.

14. The display apparatus of claim 13 , wherein the fourth gate electrode and the sixth gate electrode both contact an emission signal line.

15. The display apparatus of claim 13 , wherein the first electrode or the second electrode of the emission transistor contacts with a driving transistor without being connected to the connection electrode.

16. The display apparatus of claim 13 , wherein the first electrode or the second electrode of the reset transistor contacts with a reset voltage line without being connected to the connection electrode.

17. A driving method of a display apparatus which comprises a light emitting element comprising an anode electrode and a cathode electrode; an emission transistor comprising a second electrode connected to the anode electrode, and a first electrode and a fourth gate electrode connected to a data voltage line; and a reset transistor comprising a first electrode connected to the anode electrode, a sixth gate electrode connected to the fourth gate electrode, and a second electrode connected to a reset voltage line, wherein the cathode electrode connects to a second power source line, and the fourth gate electrode and the sixth gate electrode respectively connect to an emission control signal line, the driving method comprising:

providing a high-level emission control signal to the fourth gate electrode of the emission transistor and the sixth gate electrode of the reset transistor from the emission control signal line;

turning on the reset transistor based on the high-level emission control signal;

providing a reset voltage to the anode electrode of the light emitting element from the reset voltage line through the reset transistor; and

resetting the anode electrode based on the reset voltage.

18. The driving method of claim 17 , wherein turning on the reset transistor based on the high-level emission control signal further comprises turning off the emission transistor by the high-level emission control signal.

19. The driving method of claim 17 , further comprising:

providing a low-level emission control signal to the fourth gate electrode and the sixth gate electrode from the emission control signal line;

turning on the emission transistor based on the low-level emission control signal;

providing a data voltage to the light emitting element from the data voltage line through the emission transistor; and

emitting light from the light emitting element by the data voltage.

20. The driving method of claim 19 , wherein turning on the emission transistor based on the low-level emission control signal further comprises turning off the reset transistor using the low-level emission control signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 26, 2023
From: HWANG, JAESIK
To: LG DISPLAY CO., LTD.
Reel/Frame 065952/0563 →
Priority Claims (1)
KR 10-2022-0191295 · Dec 30, 2022 · national
Continuity (1)
Related Publication 20240221595A1 · Jul 4, 2024
References Cited (8)
US 11676528B2 · Kim et al. · 2023 [cited by applicant]
US 20140198085A1 · Park · 2014 [cited by examiner]
US 20170116925A1 · Lee · 2017 [cited by examiner]
US 20220208074A1 · Kim · 2022 [cited by examiner]
US 20230133301A1 · Chen · 2023 [cited by examiner]
US 20230267872A1 · Kim et al. · 2023 [cited by applicant]
US 20230267888A1 · Liu · 2023 [cited by examiner]
KR 1020220090924A · 2022 [cited by applicant]