Relating to methods for digital to analogue converters in surface ion traps
A surface ion trap comprising a plurality of electrodes and DACs, each electrode being controlled by a DAC, wherein a first set of DACs control the electrodes configured to trap an ion in a first area and a second set of DACs control the electrodes configured to trap an ion in a second area wherein the first set of DACs are configured to operate with low noise and low bandwidth and the second set of DACs are configured to operate with a high bandwidth and high noise.
1 . An ion trap comprising a plurality of electrodes and DACs, each electrode being controlled by a DAC, wherein a first set of DACs controls the electrodes configured to trap an ion in a first area and a second set of DACs controls the electrodes configured to trap an ion in a second area, and wherein the first set of DACs is configured to operate with low noise and the second set of DACs is configured to operate with a high bandwidth.
2 . An ion trap according to claim 1 , wherein the first set of DACs is configured to operate with low noise and low bandwidth and the second set of DACs is configured to operate with a high bandwidth and high noise.
3 . An ion trap according to claim 1 , wherein the first set of DACs is a different type of DAC from the second set of DACs.
4 . An ion trap according to claim 1 , further comprising:
an additional set of electrodes also configured to trap ions in the first area; and
a third set of DACs,
wherein each of the third set of DACs is configured to control an electrode of the additional set of electrodes, and wherein the third set of DACs is configured to operate with high bandwidth and high noise.
5 . An ion trap according to claim 4 , wherein the additional electrodes are interleaved with at least some of the plurality of electrodes.
6 . An ion trap according to claim 1 , wherein the first set of DACs is the same type of DAC as the second set of DACs, and wherein each DAC in the first set of DACs and second set of DACs comprises two modes of operation: a first mode with low noise and low bandwidth and a second mode with high noise and high bandwidth.
7 . An ion trap according to claim 6 , wherein each DAC in the first set of DACs and second set of DACs comprises an output, a first sub-DAC, and a second sub-DAC, and wherein one or more of (i) an output switch connected to one or more of the sub-DACs, (ii) a power switch connected to the one or more of the sub-DACs, or (iii) an analogue summing of the sub-DACs is configured to select the output.
8 . An ion trap according to claim 7 , wherein the first sub-DAC comprises capacitive architecture and the second sub-DAC comprises resistive architecture.
9 . An ion trap according to claim 6 , wherein each DAC in the first set of DACs and second set of DACs comprises a precision code portion for operating in the first mode with low noise and low bandwidth and a second fast code portion for operating in the second mode with high noise and high bandwidth, the ion trap further comprising a switch for switching between the precision code portion and the fast code portion.
10 . An ion trap according to claim 6 , wherein the first mode comprises a feedback loop.
11 . An ion trap according to claim 10 , wherein the feedback loop comprises a proportional integrative derivative controller configured to control the output to a reference output.
12 . An ion trap according to claim 10 , wherein the feedback loop comprises a variable gain stage.
13 . An ion trap according to claim 6 , wherein each DAC in the first set of DACs and a second set of DACs uses selectable compensation.
14 . An ion trap according to claim 1 , wherein the ion trap is a surface ion trap.
15 . An ion trap quantum computer comprising:
an ion trap comprising a plurality of electrodes and DACs, each electrode being controlled by a DAC, wherein a first set of DACs controls the electrodes configured to trap an ion in a first area and a second set of DACs controls the electrodes configured to trap an ion in a second area, and wherein the first set of DACs is configured to operate with low noise and the second set of DACs is configured to operate with a high bandwidth.