Memory Testing Techniques
Various implementations described herein refer to a device having an encoder coupled to memory. The ECC encoder receives input data from memory built-in self-test circuitry, generates encoded data by encoding the input data and by adding check bits to the input data, and writes the encoded data to memory. The device may have an ECC decoder coupled to memory. The ECC decoder reads the encoded data from memory, generates corrected data by decoding the encoded data and by extracting the check bits from the encoded data, and provides the corrected data and double-bit error flag as output. The ECC decoder has error correction logic that performs error correction on the decoded data based on the check bits, wherein if the error correction logic detects a multi-bit error in the decoded data, the error correction logic corrects the multi-bit error in the decoded data to provide the corrected data.
1 . A device, comprising:
an error correction coding (ECC) encoder coupled to memory, wherein the ECC encoder receives input data from memory built-in self-test (MBIST) circuitry, generates encoded data by encoding the input data and by adding check bits to the input data, and writes the encoded data to the memory; and
an ECC decoder coupled to the memory, wherein the ECC decoder reads the encoded data from the memory, generates corrected data by decoding the encoded data and by extracting the check bits from the encoded data, and provides the corrected data and double-bit error flag as output,
wherein the ECC decoder has error correction logic that performs error correction on the decoded data based on the check bits, wherein if the error correction logic detects a multi-bit error in the decoded data, the error correction logic corrects the multi-bit error in the decoded data to output the corrected data.
2 . The device of claim 1 , wherein the multi-bit error refers to a double-bit error.
3 . The device of claim 1 , wherein:
in response to the multi-bit error in the decoded data being less than a one-bit error, the error correction logic outputs an error flag of zero;
in response to the multi-bit error in the decoded data being equal to a one-bit error, the error correction logic corrects the one-bit error in the decoded data and outputs an error flag of zero; and
in response to the multi-bit error in the decoded data being greater than a one-bit error, the error correction logic attempts to correct the multi-bit error in the decoded data and outputs an error flag of one.
4 . The device of claim 3 , further comprising:
a replica memory built-in self-test (MBIST) that receives the corrected data and the error flag from the ECC decoder.
5 . The device of claim 4 , wherein:
in response to the error flag being zero, the replica MBIST relies on error correction coding (ECC) to correct the multi-bit error in the corrected data; and
in response to the error flag is one, the replica MBIST reverses the data sequence of the corrected data.
6 . A device, comprising:
error correction coding (ECC) circuitry comprising:
an ECC encoder being operably coupled to a memory, wherein the ECC encoder:
receives input data from MBIST (memory built-in self-testing) circuitry;
generates encoded data by adding check bits to the input data and encoding the input data; and
writes the encoded data to the memory; and
an ECC decoder being operably coupled to the memory, wherein the ECC decoder:
reads the encoded data from the memory;
generates corrected data by extracting the check bits from the encoded data and decoding the encoded data; and
provides the corrected data and a multi-bit error flag as an output.
7 . The device of claim 6 , wherein:
the ECC circuitry is configured to operate during an MBIST run where the ECC circuitry is active and at least one finite state machine (FSM) is configured to repair memory data based on the corrected data.
8 . The device of claim 6 , wherein:
in response to the encoded data being greater than the input data, check bits are added to the input bits.
9 . The device of claim 6 , wherein:
the multi-bit error flag refers to a double-bit error.
10 . The device of claim 6 , wherein:
the ECC decoder comprises error correction logic that performs error correction on the decoded data based on the check bits; and
in response to the error correction logic detecting the multi-bit error flag in the decoded data, the error correction logic corrects the multi-bit error flag in the decoded data to provide the corrected data.
11 . The device of claim 9 , wherein:
in response to the multi-bit error flag in the decoded data being less than a one-bit error, the error correction logic outputs an error flag of zero;
in response to the multi-bit error flag in the decoded data being equal to a one-bit error, the error correction logic corrects the one-bit error in the decoded data and outputs an error flag of zero; and
in response to the multi-bit error flag in the decoded data being greater than a one-bit error, the error correction logic attempts to correct the multi-bit error in the decoded data and outputs an error flag of one.
12 . The device of claim 6 , wherein:
a replica MBIST is configured to receive the corrected data and the error flag from the ECC decoder and provides output data to the MBIST circuitry.
13 . The device of claim 12 , wherein:
in response to the error flag being zero, replica MBIST error correction coding is usable to correct the multi-bit error in the corrected data; and
in response to the error flag being one, the replica MBIST reverses the data sequence of the corrected data.
14 . An integrated circuit (IC), comprising:
error correction coding (ECC) circuitry comprising:
an ECC encoder, wherein the ECC encoder:
receives input data from MBIST (memory built-in self-testing) circuitry;
generates encoded data by encoding the input data and by adding check bits to the input data; and
writes the encoded data to a memory;
an ECC decoder, wherein the ECC decoder:
reads the encoded data from the memory;
generates corrected data by decoding the encoded data and by extracting the check bits from the encoded data; and
outputs the corrected data and multi-bit error flag to a replica MBIST.
15 . The IC of claim 14 , wherein:
in response to detecting the multi-bit error flag in the decoded data, error correction logic of the ECC decoder corrects the multi-bit error flag in the decoded data to output the corrected data; and
in response to 2 or fewer bit errors being detected by the MBIST circuitry, the ECC circuitry corrects the bit errors and in response to 3 or more-bit errors being detected by the MBIST circuitry, the ECC circuitry is configured to switch to an MBIST run without ECC logic.
16 . The IC of claim 14 , wherein:
the ECC encoder is configured to input bus swap with the memory; and
the memory is configured to output bus swap with the ECC decoder.
17 . The IC of claim 14 , wherein:
the ECC circuitry is configured to conduct data error checks in multiple passes; and
a single pass comprises the input data from MBIST circuitry through the ECC circuitry, wherein the corrected data is outputted.
18 . The IC of claim 17 , wherein:
the ECC circuitry performs a first pass without bus swapping and a second pass with bus swapping to increase error detection; and
the multiple passes are configured to enhance error detection coverage and ensure comprehensive stress testing of bitcells in the memory circuitry during MBIST.
19 . The IC of claim 18 , wherein:
in the first pass the ECC encoder generates and adds the check bits to a beginning of the input data creating a first data sequence;
the MBIST circuitry is configured to test the first data sequence; and
error detection is performed by comparing the input data to the corrected data.
20 . The IC of claim 17 , wherein:
in the second pass the ECC encoder generates a second data sequence by adding the check bits to an end of the input data;
the MBIST circuitry is configured to test the second data sequence; and
error detection is performed by comparing the input data to the corrected data.