Stacked multi-gate structure and methods of fabricating the same
A semiconductor device according to the present disclosure includes a stack of first channel layers, first and second source/drain (S/D) epitaxial features adjacent to opposite sides of at least a portion of the first channel layers, respectively, a stack of second channel layers stacked over the first channel layers, third and fourth S/D epitaxial features adjacent to opposite sides of at least a portion of the second channel layers, respectively, and a dielectric isolation layer disposed under the first and second S/D epitaxial features. A total active channel layer number of the first channel layers is different from a total active channel layer number of the second channel layers. The dielectric isolation layer is in physical contact with at least a bottommost one of the first channel layers.
1. A semiconductor device, comprising:
a stack of first channel layers;
first and second source/drain (S/D) epitaxial features adjacent to opposite sides of at least a portion of the first channel layers, respectively, wherein the first and second S/D epitaxial features have a first conductivity type;
a stack of second channel layers stacked over the first channel layers;
third and fourth S/D epitaxial features adjacent to opposite sides of at least a portion of the second channel layers, respectively, wherein the third and fourth S/D epitaxial features have a second conductivity type; and
a dielectric isolation layer disposed under the first and second S/D epitaxial features,
wherein a total active channel layer number of the first channel layers is different from a total active channel layer number of the second channel layers, and wherein the dielectric isolation layer is in physical contact with at least a bottommost one of the first channel layers.
2. The semiconductor device of claim 1 , wherein the dielectric isolation layer is a first dielectric isolation layer, the semiconductor device further comprising:
a second dielectric isolation layer disposed vertically between the first and second S/D epitaxial features and the third and fourth S/D epitaxial features.
3. The semiconductor device of claim 2 , wherein the second dielectric isolation layer isolates the first and second S/D epitaxial features from physically contacting a topmost one of the first channel layers.
4. The semiconductor device of claim 2 , wherein the second dielectric isolation layer is in physical contact with the first and second S/D epitaxial features and the third and fourth S/D epitaxial features.
5. The semiconductor device of claim 1 , wherein the third and fourth S/D epitaxial features are in physical contact with a bottommost one of the second channel layers.
6. The semiconductor device of claim 1 , wherein the first and second S/D epitaxial features are in physical contact with a topmost one of the first channel layers.
7. The semiconductor device of claim 1 , wherein at least one of the first and second S/D epitaxial features has a top surface below a topmost one of the first channel layers.
8. The semiconductor device of claim 1 , further comprising:
a first power rail under the first channel layers; and
a second power rail above the second channel layers,
wherein the first and third S/D epitaxial features are electrically coupled to the first power rail, and the second and fourth S/D epitaxial features are electrically coupled to the second power rail.
9. The semiconductor device of claim 8 , wherein the third S/D epitaxial feature is directly above the first S/D epitaxial feature, and the fourth S/D epitaxial feature is directly above the second S/D epitaxial feature.
10. The semiconductor device of claim 1 , further comprising:
a first gate structure that wraps around each of the first channel layers; and
a second gate structure that wraps around each of the second channel layers.
11. A semiconductor device, comprising:
a substrate;
a first transistor over the substrate, the first transistor including first channel layers and a first source/drain (S/D) feature adjoining active members of the first channel layers;
a second transistor over the first transistor, the second transistor including second channel layers and a second S/D feature adjoining active members of the second channel layers; and
an isolation layer disposed under the first S/D feature,
wherein a number of the active members of the first channel layers is different from a number of the active members of the second channel layers, and wherein the isolation layer separates a bottommost one of the first channel layers from physically contacting the first S/D feature.
12. The semiconductor device of claim 11 , wherein a number of the first channel layers is different from a number of the second channel layers.
13. The semiconductor device of claim 11 , wherein a number of the first channel layers equals a number of the second channel layers.
14. The semiconductor device of claim 11 , wherein the number of the active members of the first channel layers is smaller than the number of the active members of the second channel layers.
15. The semiconductor device of claim 11 , wherein the first and second transistors are of opposite conductivity types.
16. The semiconductor device of claim 11 , wherein the isolation layer is in physical contact with both the bottommost one of the first channel layers and the first S/D feature.
17. The semiconductor device of claim 12 , further comprising:
a power rail under the first channel layers, wherein both of the first and second S/D features are electrically coupled to the power rail.
18. A method, comprising:
receiving a workpiece including a substrate portion and a stack portion over the substrate portion, the stack portion including a first stack of first channel layers interleaved by first sacrificial layers and a second stack of second channel layers interleaved by second sacrificial layers, the second stack being above the first stack;
forming a fin-shaped structure from the stack portion, the fin-shaped structure including a source region and a drain region;
depositing an isolation layer in the source region and the drain region, the isolation layer adjoining at least a bottommost one of the first channel layers;
after the depositing of the isolation layer, forming a first source feature in the source region and a first drain feature in the drain region; and
forming a second source feature in the source region and over the first source feature and a second drain feature in the drain region and over the first drain feature.
19. The method of claim 18 , further comprising:
prior to the forming of the second source feature and the second drain feature, depositing a dielectric layer over the first source feature and the first drain feature.
20. The method of claim 19 , wherein the dielectric layer is in physical contact with a topmost one of the first channel layers.