High voltage semiconductor device including isolation region
A high voltage semiconductor device includes an isolation region, in which multiple voids are formed in the isolation region along the vertical direction of the isolation region, so that the possibility of cracks occurring in the isolation region is minimized, and thus tungsten (W), etc. is prevented from penetrating into a space created by the cracks in a subsequent process and deteriorating the breakdown voltage characteristics.
1 . A high voltage semiconductor device, comprising:
a substrate;
an isolation region disposed in the substrate; and
a plurality of voids defined in the isolation region,
wherein the isolation region includes a DTI region extending downward, and each inner sidewall of the DTI region defines a plurality of scallops positioned along a downward direction,
wherein a horizontal width of the DTI region at a lower scallop of the plurality of scallops is less than a horizontal width of the DTI region at an upper scallop of the plurality of scallops.
2 . The high voltage semiconductor device of claim 1 , wherein each of the plurality of voids is spaced apart from another along a vertical direction in the isolation region.
3 . The high voltage semiconductor device of claim 2 ,
wherein the isolation region further comprises a pre-DTI region disposed in the substrate and on the DTI region,
wherein the plurality of voids is defined in the DTI region.
4 . The high voltage semiconductor device of claim 2 , wherein the DTI region has a trench formed by alternately performing an anisotropic etching process and an isotropic etching process, the trench having an insulating layer gap-filling the trench.
5 . A high voltage semiconductor device, comprising:
a substrate;
a gate electrode disposed on the substrate;
a drain region disposed in a surface side of the substrate;
a source region disposed in the surface side of the substrate and spaced apart from the drain region;
a body region surrounding the source region; and
an isolation region in the substrate and including a plurality of voids therein,
wherein the isolation region includes a DTI region extending downward, and each inner sidewall of the DTI region defines a plurality of scallops positioned along a downward direction,
wherein a horizontal width of the DTI region at a lower scallop of the plurality of scallops is less than a horizontal width of the DTI region at an upper scallop of the plurality of scallops.
6 . The high voltage semiconductor device of claim 5 , further comprising:
a first buried layer disposed in the substrate;
a second buried layer disposed in the substrate and below the first buried layer;
a high voltage well region connected to a side of the second buried layer; and
a deep well region disposed in the substrate and on the high voltage well region, the deep well region surrounding the drain region.
7 . The high voltage semiconductor device of claim 6 , further comprising:
a body contact region disposed in the body region, the body contact region being disposed at a side adjacent to or in contact with the source region.
8 . The high voltage semiconductor device of claim 6 , wherein each of the plurality of voids is spaced apart from another along a vertical direction in the isolation region.
9 . The high voltage semiconductor device of claim 8 , wherein a bottom void to a top void of the plurality of voids are sequentially defined in a bottom insulating layer to a top insulating layer of a plurality of insulating layers, respectively, gap-filling a trench defined in the isolation region.
10 . A high voltage semiconductor device, comprising:
a substrate; and
an isolation region disposed in the substrate and including a plurality of voids in the isolation region,
wherein the isolation region is formed by:
forming a width control layer on the substrate;
forming a trench by alternately performing an anisotropic etching process and an isotropic etching process with a predetermined number of times on a basis of a width size controlled by the width control layer; and
gap-filling the trench with an insulating layer a predetermined number of times,
wherein the isolation region includes a DTI region extending downward, and each inner sidewall of the DTI region defines a plurality of scallops positioned along a downward direction,
wherein a horizontal width of the DTI region at a lower scallop of the plurality of scallops is less than a horizontal width of the DTI region at an upper scallop of the plurality of scallops.
11 . The high voltage semiconductor device of claim 10 , wherein the width control layer includes a nitride layer.
12 . The high voltage semiconductor device of claim 10 , wherein inner sidewalls of the isolation region are inclined.