Driver and display device
A driver is disposed in a display panel, and includes a plurality of stages. At least one stage of the plurality of stages includes an input circuit which transfers an input signal to a first node in response to at least one of a clock signal and an inverted clock signal, and inverters which generate an output signal based on a voltage of the first node. At least one of the inverters includes a p-type metal-oxide-semiconductor (“PMOS”) transistor and an n-type metal-oxide-semiconductor (“NMOS”) transistor connected in series between a line transferring a relatively high gate voltage and a line transferring a relatively low gate voltage. A first active region of the PMOS transistor includes a material different from a material of a second active region of the NMOS transistor.
1. A driver disposed in a display panel, the driver including:
a plurality of stages, at least one stage of the plurality of stages comprising:
an input circuit which transfers an input signal to a first node in response to at least one of a clock signal and an inverted clock signal; and
inverters which generate an output signal based on a voltage of the first node, at least one of the inverters including:
a p-type metal-oxide-semiconductor transistor including a first active region; and
an n-type metal-oxide-semiconductor transistor including a second active region,
wherein the p-type metal-oxide-semiconductor transistor and the n-type metal-oxide-semiconductor transistor are connected in series between a line transferring a relatively high gate voltage and a line transferring a relatively low gate voltage, and
the first active region of the p-type metal-oxide-semiconductor transistor includes a material different from a material of the second active region of the n-type metal-oxide-semiconductor transistor.
2. The driver of claim 1 , wherein the first active region of the p-type metal-oxide-semiconductor transistor includes polycrystalline silicon, and
wherein the second active region of the n-type metal-oxide-semiconductor transistor includes an oxide semiconductor.
3. The driver of claim 1 , wherein the first active region of the p-type metal-oxide-semiconductor transistor includes polycrystalline silicon, and
wherein the second active region of the n-type metal-oxide-semiconductor transistor includes an organic semiconductor.
4. The driver of claim 1 , wherein the first active region of the p-type metal-oxide-semiconductor transistor includes polycrystalline silicon, and
wherein the second active region of the n-type metal-oxide-semiconductor transistor includes amorphous silicon.
5. The driver of claim 1 , wherein the first active region of the p-type metal-oxide-semiconductor transistor and the second active region of the n-type metal-oxide-semiconductor transistor are disposed in different layers, respectively, disposed at different heights, respectively, from a substrate of the display panel.
6. The driver of claim 1 , wherein the n-type metal-oxide-semiconductor transistor includes a top gate disposed above the second active region, and a bottom gate disposed below the second active region.
7. The driver of claim 6 , wherein a second relatively low gate voltage different from the relatively low gate voltage is applied to the bottom gate of the n-type metal-oxide-semiconductor transistor.
8. The driver of claim 7 , wherein the second relatively low gate voltage is lower than the relatively low gate voltage.
9. The driver of claim 6 , wherein the bottom gate of the n-type metal-oxide-semiconductor transistor is connected to the top gate of the n-type metal-oxide-semiconductor transistor.
10. The driver of claim 1 , wherein the input circuit includes:
a first p-type metal-oxide-semiconductor transistor which transfers the input signal to the first node in response to the inverted clock signal.
11. The driver of claim 1 , wherein the input circuit includes:
a first n-type metal-oxide-semiconductor transistor which transfers the input signal to the first node in response to the clock signal.
12. The driver of claim 1 , wherein the input circuit includes:
a first p-type metal-oxide-semiconductor transistor which transfers the input signal to the first node in response to the inverted clock signal; and
a first n-type metal-oxide-semiconductor transistor which transfers the input signal to the first node in response to the clock signal.
13. The driver of claim 12 , wherein the first p-type metal-oxide-semiconductor transistor includes a gate receiving the inverted clock signal, a first terminal receiving the input signal, and a second terminal connected to the first node, and
wherein the first n-type metal-oxide-semiconductor transistor includes a gate receiving the clock signal, a first terminal receiving the input signal, and a second terminal connected to the first node.
14. The driver of claim 1 , wherein the at least one stage further comprises:
a first capacitor which holds the voltage of the first node.
15. The driver of claim 14 , wherein the first capacitor includes a first electrode connected to the line transferring the relatively high gate voltage, and a second electrode connected to the first node.
16. The driver of claim 1 , wherein the inverters include:
a first complementary metal-oxide-semiconductor inverter which provides an inverted voltage to a second node by inverting the voltage of the first node; and
a second complementary metal-oxide-semiconductor inverter which generates the output signal by inverting a voltage of the second node.
17. The driver of claim 16 , wherein the first complementary metal-oxide-semiconductor inverter includes:
a second p-type metal-oxide-semiconductor transistor including a gate connected to the first node, a first terminal connected to the line transferring the relatively high gate voltage, and a second terminal connected to the second node; and
a second n-type metal-oxide-semiconductor transistor including a gate connected to the first node, a first terminal connected to the line transferring the relatively low gate voltage, and a second terminal connected to the second node, and
wherein the second complementary metal-oxide-semiconductor inverter includes:
a third p-type metal-oxide-semiconductor transistor including a gate connected to the second node, a first terminal connected to the line transferring the relatively high gate voltage, and a second terminal connected to an output node at which the output signal is output; and
a third n-type metal-oxide-semiconductor transistor including a gate connected to the second node, a first terminal connected to the line transferring the relatively low gate voltage, and a second terminal connected to the output node.
18. The driver of claim 1 , wherein the at least one stage further comprises:
a fourth p-type metal-oxide-semiconductor transistor which transfers the relatively high gate voltage to the first node in response to a global reset signal.
19. The driver of claim 18 , wherein the fourth p-type metal-oxide-semiconductor transistor includes a gate receiving the global reset signal, a first terminal connected to the line transferring the relatively high gate voltage, and a second terminal connected to the first node.
20. The driver of claim 1 , wherein the n-type metal-oxide-semiconductor transistor includes a bottom gate, and
wherein the at least one stage further comprises:
a charge pump circuit which generates a bottom gate voltage applied to the bottom gate based on the relatively low gate voltage and the clock signal.
21. The driver of claim 20 , wherein the charge pump circuit includes:
a fifth p-type metal-oxide-semiconductor transistor including a gate connected to a third node, a first terminal connected to the bottom gate, and a second terminal connected to the third node;
a sixth p-type metal-oxide-semiconductor transistor including a gate connected to the line transferring the relatively low gate voltage, a first terminal connected to the third node, and a second terminal connected to the line transferring the relatively low gate voltage;
a second capacitor including a first electrode connected to the third node, and a second electrode; and
a seventh p-type metal-oxide-semiconductor transistor including a gate connected to the third node, a first terminal connected to the second electrode of the second capacitor, and a second terminal receiving the clock signal.
22. The driver of claim 1 , wherein the inverters include:
a first complementary metal-oxide-semiconductor inverter which provides an inverted voltage to a second node by inverting the voltage of the first node; and
a second complementary metal-oxide-semiconductor inverter which generates the output signal by inverting a voltage of the second node, and
wherein the at least one stage further comprises:
an eighth p-type metal-oxide-semiconductor transistor including a gate connected to the first node, a first terminal connected to an output node at which the output signal is output, and a second terminal connected to the line transferring the relatively low gate voltage.
23. The driver of claim 1 , wherein the inverters include:
a first complementary metal-oxide-semiconductor inverter which provides an inverted voltage to a second node by inverting the voltage of the first node; and
a p-type metal-oxide-semiconductor inverter which outputs the relatively high gate voltage as the output signal when a voltage of the second node has a relatively low level, and
wherein the at least one stage further comprises:
a p-type metal-oxide-semiconductor boosting buffer which outputs the relatively low gate voltage as the output signal when the voltage of the first node has a relatively low level.
24. The driver of claim 23 , wherein the p-type metal-oxide-semiconductor boosting buffer includes:
a third capacitor including a first electrode connected to an output node at which the output signal is output, and a second electrode connected to a fourth node;
a ninth p-type metal-oxide-semiconductor transistor including a gate connected to the fourth node, a first terminal connected to the output node, and a second terminal connected to the line transferring the relatively low gate voltage; and
a tenth p-type metal-oxide-semiconductor transistor including a gate connected to the line transferring the relatively low gate voltage, a first terminal connected to the first node, and a second terminal connected to the fourth node.
25. The driver of claim 1 , wherein the inverters include:
a first complementary metal-oxide-semiconductor inverter which provides an inverted voltage to a second node by inverting the voltage of the first node; and
a second complementary metal-oxide-semiconductor inverter which generates the output signal by inverting a voltage of the second node, and
wherein the at least one stage further comprises:
a p-type metal-oxide-semiconductor boosting buffer which outputs the relatively low gate voltage as the output signal when the voltage of the first node has a relatively low level.
26. The driver of claim 1 , wherein the inverters include:
a first complementary metal-oxide-semiconductor inverter which provides an inverted voltage to a second node by inverting the voltage of the first node; and
a second complementary metal-oxide-semiconductor inverter which generates the output signal by inverting a voltage of the second node, and
wherein the at least one stage further comprises:
a third complementary metal-oxide-semiconductor inverter which generates a carry signal by inverting the voltage of the second node.
27. The driver of claim 26 , wherein the third complementary metal-oxide-semiconductor inverter includes:
an eleventh p-type metal-oxide-semiconductor transistor including a gate connected to the second node, a first terminal connected to the line transferring the relatively high gate voltage, and a second terminal connected to a carry node at which the carry signal is output; and
a fourth n-type metal-oxide-semiconductor transistor including a gate connected to the second node, a first terminal connected to the line transferring the relatively low gate voltage, and a second terminal connected to the carry node.
28. The driver of claim 26 , wherein the at least one stage further comprises:
a p-type metal-oxide-semiconductor boosting buffer which outputs the relatively low gate voltage as the output signal when the voltage of the first node has a relatively low level.
29. The driver of claim 28 , wherein the p-type metal-oxide-semiconductor boosting buffer includes:
a third capacitor including a first electrode connected to a carry node at which the carry signal is output, and a second electrode connected to a fourth node;
a ninth p-type metal-oxide-semiconductor transistor including a gate connected to the fourth node, a first terminal connected to an output node at which the output signal is output, and a second terminal connected to the line transferring the relatively low gate voltage; and
a tenth p-type metal-oxide-semiconductor transistor including a gate connected to the line transferring the relatively low gate voltage, a first terminal connected to the first node, and a second terminal connected to the fourth node.
30. The driver of claim 1 , wherein the inverters include:
a first complementary metal-oxide-semiconductor inverter which provides an inverted voltage to a second node by inverting the voltage of the first node; and
a p-type metal-oxide-semiconductor inverter which outputs the relatively high gate voltage as the output signal when a voltage of the second node has a relatively low level, and
wherein the at least one stage further comprises:
a p-type metal-oxide-semiconductor boosting buffer which outputs the relatively low gate voltage as the output signal when the voltage of the first node has a relatively low level; and
a third complementary metal-oxide-semiconductor inverter which generates a carry signal by inverting the voltage of the second node.
31. A driver disposed in a display panel, the driver including:
a plurality of stages, at least one stage of the plurality of stages comprising:
an input circuit which transfers an input signal to a first node in response to at least one of a clock signal and an inverted clock signal; and
inverters which generate an output signal based on a voltage of the first node, at least one of the inverters includes:
a p-type metal-oxide-semiconductor transistor; and
an n-type metal-oxide-semiconductor transistor including:
an active region;
a top gate disposed above the active region; and
a bottom gate disposed below the active region,
wherein the p-type metal-oxide-semiconductor transistor and the n-type metal-oxide-semiconductor transistor are connected in series between a line transferring a relatively high gate voltage and a line transferring a relatively low gate voltage.
32. The driver of claim 31 , wherein a second relatively low gate voltage different from the relatively low gate voltage is applied to the bottom gate of the n-type metal-oxide-semiconductor transistor.
33. The driver of claim 31 , wherein the bottom gate of the n-type metal-oxide-semiconductor transistor is connected to the top gate of the n-type metal-oxide-semiconductor transistor.
34. The driver of claim 31 , wherein an active region of the p-type metal-oxide-semiconductor transistor includes a material different from a material of the active region of the n-type metal-oxide-semiconductor transistor.
35. A display device comprising:
a display panel including a plurality of pixels;
a data driver which provides data signals to the plurality of pixels;
a gate driver which provides gate signals to the plurality of pixels;
an emission driver which provides emission signals to the plurality of pixels; and
a controller which controls the data driver, the gate driver and the emission driver,
wherein at least one of the gate driver and the emission driver includes a plurality of stages, and
wherein at least one stage of the plurality of stages comprising:
an input circuit which transfers an input signal to a first node in response to at least one of a clock signal and an inverted clock signal; and
inverters which generate an output signal corresponding to one of the gate signals or one of the emission signals based on a voltage of the first node,
wherein at least one of the inverters includes a p-type metal-oxide-semiconductor transistor and an n-type metal-oxide-semiconductor transistor connected in series between a line transferring a relatively high gate voltage and a line transferring a relatively low gate voltage, and
wherein a first active region of the p-type metal-oxide-semiconductor transistor includes a material different from a material of a second active region of the n-type metal-oxide-semiconductor transistor.