Memory devices with dual-side access circuits and methods for operating the same

1. A memory circuit, comprising:

a memory array comprising a plurality of non-volatile memory cells, wherein the non-volatile memory cells are arranged along a plurality of access lines that extend along a lateral direction;

a first access circuit physically disposed on a first side of the memory array in the lateral direction; and

a second access circuit physically disposed on a second side of the memory array in the lateral direction, the second side being opposite to the first side;

wherein when each of the non-volatile memory cells is configured to be programmed by at least a first current and a second current, the first current and second current flow through a first path and a second path, respectively, and wherein the first path at least comprises a portion on the first side and the second path at least comprises a portion on the second side.

2. The memory circuit of claim 1 , wherein each of the non-volatile memory cells comprises a magnetic tunnel junction (MTJ) element.

3. The memory circuit of claim 1 , wherein the first access circuit comprises a first sub-circuit and a second sub-circuit, and the second access circuit comprises a third sub-circuit, and wherein the first sub-circuit and the second sub-circuit operatively form a portion of the first path, and the first sub-circuit and the third sub-circuit operatively form a portion of the second path.

4. The memory circuit of claim 3 , wherein the first sub-circuit is configured to couple a programming voltage through a corresponding one of the access lines to a corresponding one of the non-volatile memory cells, while the second sub-circuit and the third sub-circuit are configured to couple the first path and the second path to ground, respectively.

5. The memory circuit of claim 1 , wherein the first access circuit comprises a first sub-circuit, and the second access circuit comprises a second sub-circuit and a third sub-circuit, and wherein the first sub-circuit and the third sub-circuit operatively form a portion of the first path, and the second sub-circuit and the third sub-circuit operatively form a portion of the second path.

6. The memory circuit of claim 5 , wherein the first sub-circuit and the second sub-circuit are each configured to couple a programming voltage through a corresponding one of the access lines to a corresponding one of the non-volatile memory cells, while the third sub-circuit is configured to couple the first path and the second path to ground.

7. The memory circuit of claim 1 , wherein the first access circuit comprises a first sub-circuit and a second sub-circuit, and the second access circuit comprises a third sub-circuit, and wherein the first sub-circuit and the second sub-circuit operatively form a portion of the first path, and the third sub-circuit and the second sub-circuit operatively form a portion of the second path.

8. The memory circuit of claim 7 , wherein the first sub-circuit and the third sub-circuit are each configured to couple a programming voltage through a corresponding one of the access lines to a corresponding one of the non-volatile memory cells, while the second sub-circuit is configured to couple the first path and the second path to ground.

9. The memory circuit of claim 1 , wherein the first access circuit comprises a first sub-circuit and a second sub-circuit, and the second access circuit comprises a third sub-circuit and a fourth sub-circuit, and wherein the first sub-circuit and the second sub-circuit operatively form a portion of the first path, and the third sub-circuit and the fourth sub-circuit operatively form a portion of the second path.

10. The memory circuit of claim 9 , wherein the first sub-circuit and the third sub-circuit are each configured to couple a programming voltage through a corresponding one of the access lines to a corresponding one of the non-volatile memory cells, while the second sub-circuit and the fourth sub-circuit are configured to couple the first path and the second path to ground, respectively.

11. The memory circuit of claim 1 , wherein the first path and the second path both extend from the first or second side, both extend through a corresponding one of the non-volatile memory cells, and then separate toward the first side and the second side, respectively.

12. The memory circuit of claim 1 , wherein the first path and the second path extend from the first side and the second side, respectively, both extend through a corresponding one of the non-volatile memory cells, and then both extend toward the first or second side.

13. The memory circuit of claim 1 , wherein the first current and the second current have a same direction, and the direction is configured to determine a logic state programmed into a corresponding one of the non-volatile memory cells.

14. A memory circuit, comprising:

a plurality of non-volatile memory cells arranged over a plurality of bit lines that extend along a lateral direction;

a first access circuit physically disposed on a first side of the non-volatile memory cells in the lateral direction, wherein the first access circuit comprises a first sub-circuit and a second sub-circuit; and

a second access circuit physically disposed on a second side of the non-volatile memory cells in the lateral direction, the second side being opposite to the first side, wherein the second access circuit comprises a third sub-circuit and a fourth sub-circuit;

wherein the first sub-circuit is configured to couple a programming voltage to a corresponding one of the plurality of non-volatile memory cells and the second and fourth sub-circuits are each configured to complement a conduction path from the programming voltage to ground, when programming a first logic state to the corresponding non-volatile memory cell; and

wherein the second sub-circuit is configured to couple the programming voltage to the corresponding non-volatile memory cell and the first and third sub-circuits are each configured to complement another conduction path from the programming voltage to the ground, when programming a second logic state to the corresponding non-volatile memory cell.

15. The memory circuit of claim 14 , wherein each of the non-volatile memory cells comprises a magnetic tunnel junction (MTJ) element.

16. The memory circuit of claim 14 , wherein the first sub-circuit and the second sub-circuit each include one or more first switches coupled between a corresponding one of the bit lines and the corresponding non-volatile memory cell.

17. The memory circuit of claim 16 , wherein the first sub-circuit and the second sub-circuit each include one or more second switches coupled between the corresponding non-volatile memory cell and ground.

18. The memory circuit of claim 17 , wherein the third sub-circuit and the fourth sub-circuit each include one or more third switches coupled between the corresponding non-volatile memory cell and ground.

19. A method for operating a memory circuit, comprising:

activating (i) a first access circuit physically disposed on a first side of a non-volatile memory cell; (ii) a second access circuit physically disposed on the first side of the non-volatile memory cell; and (iii) a third access circuit physically disposed on a second side of the non-volatile memory cell;

providing a voltage to the non-volatile memory cell;

conducting a first current flowing through a first conduction path that extends from the voltage, through the first access circuit, the non-volatile memory cell, and the second access circuit, and to ground; and

conducting a second current flowing through a second conduction path that extends from the programming voltage, through the first access circuit, the non-volatile memory cell, and the third access circuit, and to ground.

20. The method of claim 19 , wherein the non-volatile memory cell comprises a magnetic tunnel junction (MTJ) element.