High performance processor for low-way and high-latency memory instances
Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.
1. A method performed for operating a distributed memory device comprising:
determining a number of words that are required simultaneously to perform a task, the task requiring at least one computation, and
providing instructions for writing words that need to be accessed simultaneously in a plurality of memory banks when a number of words that can be accessed simultaneously from one of the plurality of memory banks is lower than the number of words that are required simultaneously;
receiving, by a configuration manager, an indication to perform the task; and
in response to receiving the indication, configuring a memory controller to:
within a first line access cycle:
access at least one first word from a first memory bank from the plurality of memory banks using a first memory line,
send the at least one first word to at least one processing unit connected to the memory controller, and
open a first memory line in a second memory bank to access a second address from the second memory bank from the plurality of memory banks, and
within a second line access cycle:
access at least one second word from the second memory bank using the first memory line,
send the at least one second word to at least one processing unit connected to the memory controller, and
access a third address from the first memory bank using a second memory line in the first memory bank.
2. The method of claim 1 , further comprising:
determining a number of cycles necessary to perform the task; and
writing words that are needed in sequential cycles in a single memory bank of the plurality of memory banks.
3. The method of claim 1 , further configuring a selected processing unit to transfer data to the second memory bank during the first line access cycle.
4. The method of claim 1 , wherein
the memory controller comprises at least two data inputs from the plurality of memory banks and at least two data outputs connected to each one of the at least one processing unit; and
further comprising configuring the memory controller to:
simultaneously receive data from two memory banks via the two data inputs; and
simultaneously transmit data received via the two data inputs to at least one selected processing unit via the two data outputs.
5. The method of claim 1 , further comprising:
when a number a number of words that can be accessed simultaneously from one of the plurality of memory banks is lower than the number of words that are required simultaneously, divide the number of words required simultaneously between multiple memory banks.
6. The method of claim 1 , wherein the configuration manager comprises a local memory that stores a command to be transmitted to at least one of a plurality of processing units.
7. The method of claim 1 , further comprising configuring the memory controller to interrupt the task in response to receiving a request from an external interface.
8. The method of claim 1 , further comprising configuring the configuration manger and the at least one processing unit to hand over access to the memory controller between each other after finalizing a task.
9. A non-transitory computer-readable medium that stores instructions that, when executed by at least one processor, cause the at least one processor to:
determine a number of words that are required simultaneously to perform a task, the task requiring at least one computation;
write words that need to be accessed simultaneously in a plurality of memory banks when a number of words that can be accessed simultaneously from one of the plurality of memory banks is lower than the number of words that are required simultaneously;
transmit an indication to perform the task to a configuration manager; and
transmit instructions to configure a memory controller to:
within a first line access cycle:
access at least one first word from a first memory bank from the plurality of memory banks using a first memory line,
send the at least one first word to at least one processing unit connected to the memory controller, and
open a first memory line in a second memory bank to access a second address from the second memory bank from the plurality of memory banks, and
within a second line access cycle:
access at least one second word from the second memory bank using the first memory line,
send the at least one second word to at least one processing unit connected to the memory controller, and
access a third address from the first memory bank using a second memory line in the first memory bank.
10. The non-transitory computer-readable medium of claim 9 , wherein a selected processing unit is configured to transfer data to the second memory bank during the first line access cycle.
11. The non-transitory computer-readable medium of claim 9 , wherein
the memory controller comprises at least two data inputs from the plurality of memory banks and at least two data outputs connected to each one of the at least one processing unit;
the memory controller is configured to simultaneously receive data from two memory banks via the two data inputs; and
the memory controller is configured to simultaneously transmit data received via the two data inputs to at least one selected processing unit via the two data outputs.
12. The non-transitory computer-readable medium of claim 9 , wherein the at least one processing unit comprises a plurality of accelerators configured for pre-defined tasks.
13. The non-transitory computer-readable medium of claim 12 , wherein the plurality of accelerators comprise at least one of a vector multiply accumulate unit or a direct memory access.
14. The non-transitory computer-readable medium of claim 9 , wherein the configuration manager comprises at least one of a RISC processor or a micro-controller.
15. The non-transitory computer-readable medium of claim 9 , further comprising an external interface connected to the plurality of memory banks.
16. The non-transitory computer-readable medium of claim 9 , when a number a number of words that can be accessed simultaneously from one of the plurality of memory banks is lower than the number of words that are required simultaneously, divide the number of words required simultaneously between multiple memory banks.
17. The non-transitory computer-readable medium of claim 9 , wherein the words comprise machine instructions.
18. The non-transitory computer-readable medium of claim 9 , wherein the configuration manager comprises a local memory that stores a command to be transmitted to at least one of the at least one processing unit.
19. The non-transitory computer-readable medium of claim 9 , wherein the plurality of memory banks includes at least one of DRAM mats, DRAM, banks, flash mats, or SRAM mats.
20. The non-transitory computer-readable medium of claim 9 , wherein the at least one processing unit comprises at least one arithmetic logic unit, at least one vector handling logic unit, at least one register, and at least one direct memory access.