Virtualized-in-hardware Input Output Memory Management
Aspects relate to Input/Output (IO) Memory Management Units (MMUs) that include hardware structures for implementing virtualization. Some implementations allow guests to setup and maintain device IO tables within memory regions to which those guests have been given permissions by a hypervisor. Some implementations provide hardware page table walking capability within the IOMMU, while other implementations provide static tables. Such static tables may be maintained by a hypervisor on behalf of guests. Some implementations reduce a frequency of interrupts or invocation of hypervisor by allowing transactions to be setup by guests without hypervisor involvement within their assigned device IO regions. Devices may communicate with IOMMU to setup the requested memory transaction, and completion thereof may be signaled to the guest without hypervisor involvement. Various other aspects will be evident from the disclosure.
1 . An apparatus comprising:
a physical processor element capable of being configured to execute a hypervisor that hosts one or more guest Operating Systems (OS) by presenting a respective virtualized machine interface to each hosted guest OS;
a physical memory;
an Input/Output (I/O) device; and
an I/O Memory Management Unit (IOMMU) coupled to the physical processor element, the IOMMU configured to:
receive from the hypervisor a direct mapping between a guest address for a hosted guest OS, and an address in the physical memory;
store a mapping in a device table between a guest identifier for the guest OS and an identifier for the I/O device;
access an IOMMU command queue managed by the hypervisor;
read and interpret one or more commands from the IOMMU command queue, wherein the read is cached coherent so that each command is removed from the IOMMU after interpretation; and
write to an error log managed by the IOMMU, wherein each error-log write by the IOMMU is defined at least in part by a cached-coherent write attribute of the IOMMU.
2 . The apparatus of claim 1 , wherein the IOMMU is further configured to process a direct memory access request from the I/O device in accordance with a cached-coherent attribute associated with the request.
3 . The apparatus of claim 2 , wherein the IOMMU is further configured to modify, in response to a command from the hypervisor, the cached-coherent attribute associated with the request from a non-coherent attribute to a coherent attribute.
4 . The apparatus of claim 1 , wherein one or more commands are inserted by a hypervisor to into the command queue using a command queue tail pointer.
5 . The apparatus of claim 4 , wherein the IOMMU is further configured to read a command from the command queue using a command queue head pointer.
6 . The apparatus of claim 5 , wherein the IOMMU is further configured to determine whether a command is present in the command queue based on a difference between the command queue tail pointer and the command queue head pointer.
7 . The apparatus of claim 1 , wherein the IOMMU is further configured to store the direct mapping in a Translation Lookaside Buffer (TLB) maintained within the IOMMU, wherein the hypervisor manages contents of the TLB.
8 . An Input/Output Memory Management Unit (IOMMU) comprising:
a device table storing entries mapping respective identifiers to respective I/O devices, each guest identifier identifying one of one or more Guest Operating Systems (OS) executing on a processor coupled with the IOMMU, and indicating read and writing permissions to be accorded the I/O device; and
circuitry configured to:
receive from the hypervisor a direct mapping between a guest address for a hosted guest OS, and an address in a physical memory;
access an IOMMU command queue managed by the hypervisor;
read and interpret one or more commands from the IOMMU command queue, wherein the read is cached coherent so that each command is removed from the IOMMU after interpretation; and
write to an error log managed by the IOMMU, wherein each error-log write by the IOMMU is defined at least in part by a cached-coherent write attribute of the IOMMU.
9 . The IOMMU of claim 8 , wherein the circuitry is further configured to process a direct memory access request from the I/O device in accordance with a cached-coherent attribute associated with the request.
10 . The IOMMU of claim 8 , wherein the circuitry is further configured to modify, in response to a command from the hypervisor, the cached-coherent attribute associated with the request from a non-coherent attribute to a coherent attribute.
11 . The IOMMU of claim 8 , wherein one or more commands are inserted by a hypervisor to into the command queue using a command queue tail pointer.
12 . The IOMMU of claim 11 , wherein the circuitry is further configured to read a command from the command queue through a command queue head pointer.
13 . The IOMMU of claim 12 , wherein the circuitry is further configured to determine whether a command is present in the command queue based on a difference between the command queue tail pointer and the command queue head pointer.
14 . The IOMMU of claim 8 , wherein the circuitry is further configured to store the direct mapping in a Translation Lookaside Buffer (TLB) maintained within the IOMMU, wherein the hypervisor manages contents of the TLB.