Three-level inverter power module with multiple operation modes
A three-level T-type neutral point clamp (TNPC) inverter comprises: a first direct current (DC) terminal and a second DC terminal; a first capacitor and a second capacitor electrically connected in series between the first and second DC terminals; and first, second and third circuitry legs, each of the first, second and third circuitry legs including i) switches electrically connected in series between the first and second DC terminals, and ii) a T-leg switch electrically connected between a point between the first and second capacitors and a point between the switches, wherein the T-leg switch is undersized compared to the switches.
1 . A three-level T-type neutral point clamp (TNPC) inverter comprising:
a first direct current (DC) terminal and a second DC terminal;
a first capacitor and a second capacitor electrically connected in series between the first and second DC terminals; and
first, second and third circuitry legs, each of the first, second and third circuitry legs including i) switches electrically connected in series between the first and second DC terminals, and ii) a T-leg switch electrically connected between a point between the first and second capacitors and a point between the switches, wherein the T-leg switch is undersized compared to the switches, wherein the T-leg switch is undersized compared to the switches by the T-leg switch having less die area than a die area of each of the switches, and wherein the die area of the T-leg switch is at most about 20 percent of the die area of each of the switches.
2 . The three-level TNPC inverter of claim 1 , wherein each of the switches is an insulated-gate bipolar transistor (IGBT).
3 . The three-level TNPC inverter of claim 2 , wherein the T-leg switch comprises at least two T-leg switches arranged to perform blocking.
4 . The three-level TNPC inverter of claim 2 , wherein the T-leg switch comprises a bidirectional HEMT.
5 . The three-level TNPC inverter of claim 4 , wherein the T-leg switch is a GaN HEMT.
6 . The three-level TNPC inverter of claim 1 , wherein each of the switches is a metal-oxide-semiconductor field-effect transistor (MOSFET).
7 . The three-level TNPC inverter of claim 6 , wherein each of the switches is a silicon MOSFET.
8 . The three-level TNPC inverter of claim 6 , wherein each of the switches is a silicon-carbide MOSFET.
9 . The three-level TNPC inverter of claim 1 , wherein each of the switches is a HEMT.
10 . The three-level TNPC inverter of claim 9 , wherein the T-leg switch is a HEMT.
11 . The three-level TNPC inverter of claim 10 , wherein the T-leg switch comprises at least two T-leg switches arranged to perform blocking, and wherein the two T-leg switches are HEMTs.
12 . The three-level TNPC inverter of claim 1 , wherein the T-leg switch is undersized compared to the switches by the T-leg switch being implemented using fewer dies, or being implemented using smaller dies, or both, than each of the switches.
13 . A three-level T-type neutral point clamp (TNPC) inverter comprising:
a first direct current (DC) terminal and a second DC terminal;
a first capacitor and a second capacitor electrically connected in series between the first and second DC terminals; and
first, second and third circuitry legs, each of the first, second and third circuitry legs including i) switches electrically connected in series between the first and second DC terminals, and ii) a T-leg switch electrically connected between a point between the first and second capacitors and a point between the switches, wherein the T-leg switch is undersized compared to the switches, wherein the T-leg switch is undersized compared to the switches by the T-leg switch having a current rating that is lower than a current rating of each of the switches, and wherein the current rating of the T-leg switch is at most about 20 percent of the current rating of each of the switches.
14 . The three-level TNPC inverter of claim 13 , wherein the T-leg switch comprises a bidirectional HEMT.
15 . The three-level TNPC inverter of claim 14 , wherein the T-leg switch is a GaN HEMT.
16 . The three-level TNPC inverter of claim 13 , wherein each of the switches is a metal-oxide-semiconductor field-effect transistor (MOSFET).
17 . The three-level TNPC inverter of claim 16 , wherein each of the switches is a silicon MOSFET.
18 . The three-level TNPC inverter of claim 16 , wherein each of the switches is a silicon-carbide MOSFET.
19 . The three-level TNPC inverter of claim 13 , wherein each of the switches is a HEMT.
20 . The three-level TNPC inverter of claim 13 , wherein the T-leg switch is a HEMT.
21 . The three-level TNPC inverter of claim 20 , wherein the T-leg switch comprises at least two T-leg switches arranged to perform blocking, and wherein the two T-leg switches are HEMTs.
22 . The three-level TNPC inverter of claim 13 , wherein the T-leg switch is undersized compared to the switches by the T-leg switch being implemented using fewer dies, or being implemented using smaller dies, or both, than each of the switches.