Method, device, and circuit for high-speed memories
View Patent ↗In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a plurality of memory cells arranged in an array, an input/output (I/O) interface connected to the plurality of memory cells to output data signal from each memory cell, and a control circuit. In some embodiments, the control circuit includes a first clock generator to generate a first clock signal and a second clock signal according to an input clock signal and a chip enable (CE) signal and provide the first clock signal to the plurality of memory cells. In some embodiments, the control circuit includes a second clock generator to generate a third clock signal according to the input clock signal and a DFT (design for testability) enable signal. In some embodiments, the control circuit generates an output clock signal according to the second clock signal or the third clock signal.
1. A control circuit, comprising:
a first clock generator configured to generate a mission mode clock (MDCK) signal according to an input clock signal and a chip enable (CE) signal; and
a second clock generator configured to generate a design for testability (DFT) mode clock (DDCK) signal according to the input clock signal and provide the first clock generator with a DFT enable (DFTEN) signal;
wherein in response to the DFTEN signal being in a high logic state, an output clock signal, provided by the control circuit, follows the DDCK signal, and in response to the DFTEN signal being in a low logic state, the output clock signal follows the MDCK signal.
2. The control circuit of claim 1 , further comprising a logic gate configured to perform a logic OR operation on the MDCK signal and the DDCK signal to generate the output clock signal.
3. The control circuit of claim 1 , wherein the DFTEN signal is generated by performing a logic OR operation on a scan enable (SE) signal and a DFT bypass (DFTBYP) signal.
4. The control circuit of claim 1 , further comprising a logic gate configured to perform a logic NOR on the MDCK signal and the DDCK signal to generate a first clock signal, and the first clock signal passes through an inverter to generate the output clock signal.
5. The control circuit of claim 1 , wherein the MDCK signal passes through a first inverter to generate a first clock signal, the DDCK signal passes through a second inverter to generate a second clock signal, and the control circuit performs a logic NAND on the first clock signal and the second clock signal to generate the output clock signal.
6. The control circuit of claim 1 , wherein the second clock generator provides a buffered DFTEN signal to the first clock generator.
7. The control circuit of claim 1 , wherein the second clock generator generates the DDCK signal according to the input clock signal, the DFTEN signal, and an initialization (INIT) signal.
8. The control circuit of claim 1 , wherein the first clock generator generates a global clock (GCK) signal according to the input clock signal and the chip enable (CE) signal, and provide the GCK signal to a plurality of memory cells.
9. A memory device, comprising:
a plurality of memory cells arranged in an array;
an input/output (I/O) interface, connected to the plurality of memory cells to output data signal from each memory cell; and
a control circuit, comprising:
a first clock generator configured to generate a mission mode clock (MDCK) signal according to an input clock signal and a chip enable (CE) signal; and
a second clock generator configured to generate a design for testability (DFT) mode clock (DDCK) signal according to the input clock signal and provide the first clock generator with a DFT enable (DFTEN) signal;
wherein in response to the DFTEN signal being in a high logic state, an output clock signal, provided by the control circuit, follows the DDCK signal, and in response to the DFTEN signal being in a low logic state, the output clock signal follows the MDCK signal.
10. The memory device of claim 9 , further comprising a logic gate configured to perform a logic OR operation on the MDCK signal and the DDCK signal to generate the output clock signal.
11. The memory device of claim 9 , wherein the DFTEN signal is generated by performing a logic OR operation on a scan enable (SE) signal and a DFT bypass (DFTBYP) signal.
12. The memory device of claim 9 , wherein the control circuit is configured to perform a logic NOR on the MDCK signal and the DDCK signal to generate a first clock signal, and the first clock signal passes through an inverter to generate the output clock signal.
13. The memory device of claim 9 , wherein the MDCK signal passes through a first inverter to generate a first clock signal, the DDCK signal passes through a second inverter to generate a second clock signal, and the control circuit performs a logic NAND on the first clock signal and the second clock signal to generate the output clock signal.
14. The memory device of claim 9 , wherein the second clock generator provides a buffered DFTEN signal to the first clock generator.
15. The memory device of claim 9 , wherein the second clock generator generates the DDCK signal according to the input clock signal, the DFTEN signal, and an initialization (INIT) signal.
16. The memory device of claim 9 , wherein the first clock generator generates a global clock (GCK) signal according to the input clock signal and the chip enable (CE) signal, and provide the GCK signal to the plurality of memory cells.
17. A control circuit, comprising:
a first clock generator configured to generate a mission mode clock (MDCK) signal according to an input clock signal and a chip enable (CE) signal;
a second clock generator configured to generate a design for testability (DFT) mode clock (DDCK) signal according to the input clock signal and provide the first clock generator with a DFT enable (DFTEN) signal; and
a logic gate configured to generate an output clock signal based on the DDCK signal and the MDCK signal;
wherein in response to the DFTEN signal being in a high logic state, the output clock signal follows the DDCK signal, and in response to the DFTEN signal being in a low logic state, the output clock signal follows the MDCK signal.
18. The control circuit of claim 17 , wherein the logic gate is configured to perform a logic OR operation on the MDCK signal and the DDCK signal to generate the output clock signal.
19. The control circuit of claim 17 , wherein the logic gate is configured to perform a logic NOR operation on the MDCK signal and the DDCK signal to generate the output clock signal through an inverter.
20. The control circuit of claim 17 , further comprising:
a first inverter configured to logically invert the MDCK signal; and
a second inverter configured to logically invert the DDCK signal;
wherein the logic gate is configured to perform a logic NAND operation on the inverted MDCK signal and the inverted DDCK signal to generate the output clock signal.