Memory device and method for operating the same
A memory device and a method for operating a memory device are provided. The memory device includes a stack structure including a memory array stack and a staircase stack, an insulating film on the memory array stack, a conductive film on the staircase stack and on a sidewall of the insulating film, a pillar element on the staircase stack and passing through the conductive film, and memory cells in the memory array stack and electrically connected to the pillar element.
1 . A memory device, comprising:
a stack structure comprising a memory array stack and a staircase stack;
an insulating film on the memory array stack along a first direction;
a conductive film on the staircase stack and on a sidewall of the insulating film;
a pillar element on the staircase stack and passing through the conductive film; and
memory cells in the memory array stack and electrically connected to the pillar element,
wherein the conductive film and the insulating film are disposed along a second direction perpendicular to the first direction.
2 . The memory device according to claim 1 , wherein the pillar element comprises a dielectric element and a channel element, and the dielectric element is between the channel element and the conductive film.
3 . The memory device according to claim 2 , wherein the conductive film, the dielectric element and the channel element forms a transistor switch.
4 . The memory device according to claim 2 , wherein the conductive film, the dielectric element and the channel element forms a word line switch.
5 . The memory device according to claim 2 , wherein the channel element extends beyond an upper surface and a lower surface of the conductive film.
6 . The memory device according to claim 1 , wherein the pillar element comprises a first pillar portion, a second pillar portion and a third pillar portion electrically connected to each other, the second pillar portion is between the first pillar portion and a third pillar portion, the second pillar portion comprises a dielectric element, a channel element and a pad, the dielectric element surrounds the channel element, and the pad is between the channel element and the third pillar portion.
7 . The memory device according to claim 1 , wherein the first pillar portion has a first end and a second end opposite to the first end, the first end is on an upper surface of the staircase stack, and the second end connects to the second pillar portion.
8 . The memory device according to claim 1 , wherein the pillar element extends along the first direction and passes through the conductive film, the insulating film overlaps the memory array stack in the first direction, and the conductive film overlaps the staircase stack in the first direction.
9 . The memory device according to claim 1 , further comprising:
a pillar structure comprising an ovonic material layer and passing through the memory array stack.
10 . The memory device according to claim 9 , wherein the pillar structure comprises an electrode layer on an inner surface or an outer surface of the ovonic material layer.
11 . The memory device according to claim 9 , wherein the pillar structure comprises a first electrode layer and a second electrode layer, the ovonic material layer is between the first electrode layer and the second electrode layer.
12 . The memory device according to claim 9 , wherein the pillar structure comprises a conductive pillar surrounded by the ovonic material layer, the conductive pillar is functioned as a bit line connected to the memory cells.
13 . The memory device according to claim 9 , wherein an upper surface of the pillar structure is higher than an upper surface of the conductive film.
14 . The memory device according to claim 1 , wherein when operating the memory device to turn on a selected memory cell of the memory cells, a bias direction of a voltage applied to a bit line electrically connected to the selected memory cell in RESET operation procedure is opposite to a bias direction of a voltage applied to the bit line electrically connected to the selected memory cell in SET operation procedure.
15 . The memory device according to claim 1 , further comprising:
a wire on the conductive film and electrically connected to the pillar element, wherein the wire extends along a third direction; and
another conductive film, wherein the conductive film and the another conductive film are arranged apart from each other along the third direction, wherein the first direction, the second direction and the third direction are perpendicular to each other.
16 . A method for operating a memory device according to claim 1 , the memory device comprises memory cells, a plurality of bit lines electrically connected to the memory cells, a plurality of word lines electrically connected to the memory cells, and a plurality of word line switches electrically connected to the memory cells and the plurality of word lines, wherein the method comprises:
applying a word line voltage to a word line of the plurality of word lines electrically connected to a selected memory cell of the memory cells, applying a control voltage to a word line switch of the plurality of word line switches electrically connected to the selected memory cell, and applying a bit line voltage to a bit line of the plurality of bit lines electrically connected to the selected memory cell to turn on the selected memory cell,
wherein the word line switch and the bit line are controlled independently.
17 . The method according to claim 16 , further comprising:
applying a ground voltage to word lines of the plurality of word lines electrically connected to unselected memory cells of the memory cells, apply a ground control voltage to word line switches of the plurality of word line switches electrically connected to the unselected memory cells, and applying a ground voltage to bit lines of the plurality of bit lines electrically connected to the unselected memory cells to turn off the unselected memory cells.
18 . The method according to claim 16 , wherein the memory device comprises ovonic material layers surrounding the plurality of bit lines.
19 . The method according to claim 16 , wherein the memory device comprises:
a stack structure comprising a memory array stack and a staircase stack;
an insulating film on the memory array stack;
a conductive film on the staircase stack and on a sidewall of the insulating film; and
a pillar element on the staircase stack and passing through the conductive film,
wherein the memory cells are in the memory array stack and electrically connected to the pillar element.
20 . The method according to claim 16 , wherein the bit line voltage comprises a first bit line voltage and a second bit line voltage, the first bit line voltage is applied to the bit line of the plurality of bit lines electrically connected to the selected memory cell to turn on the selected memory cell to perform a RESET operation procedure, the second bit line voltage is applied to the bit line of the plurality of bit lines electrically connected to the selected memory cell to turn on the selected memory cell to perform a SET operation procedure, a bias direction of the first bit line voltage is opposite to a bias direction of the second bit line voltage.