Heterogenous interleaved Reed-Solomon (HetIRS) with erasure decoding
Provided is a memory system comprising a plurality of memory components. The ECC decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ECC) decoding on the first and second codewords received read from the plurality of memory components wherein the ECC decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.
1 . A memory system comprising:
a plurality of memory components; and
a controller in communication with the plurality of memory components and configured to:
receive a data block and partition the data block into a plurality of memory segments distributed across the plurality of memory components;
construct first and second codewords from a same set of data bits derived from the data block; and
perform error correction code (ECC) decoding on the first and second codewords that were received and read from the plurality of memory components;
wherein the ECC decoding is configured to:
(i) detect random errors in the first codeword using a first ECC decoding scheme, and
(ii) use corrected data bits from decoding the first codeword to correct erasures in the second received codeword using a second ECC decoding scheme,
wherein the first and second codewords are associated by being derived from the same data block and are encoded using complementary ECC mechanisms that enable decoding of the second codeword using results from decoding the first codeword.
2 . The memory system of claim 1 , wherein the ECC decoding includes calculating syndromes of the first and second codewords.
3 . The memory system of claim 2 , wherein the ECC decoding includes calculating error locate polynomials (ELPs) from the calculated syndromes.
4 . The memory system of claim 3 , wherein the ECC decoding includes deriving polynomial root values from the calculate ELPs.
5 . The memory system of claim 1 , wherein the random errors include at least one of bit and symbol errors.
6 . The memory system of claim 1 , wherein the plurality of memory components includes dynamic random access memory (DRAM) devices.
7 . The memory system of claim 6 , wherein the memory system is constructed in accordance compute express link (CXL) principles.
8 . The memory system of claim 7 , wherein the ECC decoding is performed in accordance with Reed Solomon (RS) codes.
9 . The memory system of claim 1 , wherein one portion of each of the received first and second codewords includes data symbols and a remaining portion of the received word includes parity symbols.
10 . A method comprising:
receiving a data block and partitioning the data block into a plurality of memory segments distributed across a plurality of memory components;
constructing, via a plurality of memory components in communication with a controller, first and second codewords from a same set of data bits derived from the data block; and
performing error correction code (ECC) decoding on the first and second codewords that are received and read from the plurality of memory components;
wherein the ECC decoding is configured to:
(i) detect random errors in the first codeword using a first ECC decoding scheme, and
(ii) use corrected data bits from decoding the first codeword to correct erasures in the second codeword using a second ECC decoding scheme,
wherein the first and second codewords are associated by being derived from the same data block and are encoded using complementary ECC mechanisms that enable decoding of the second codeword using results from decoding the first codeword.
11 . The method system of claim 10 , wherein the ECC decoding includes calculating syndromes of the first and second codewords.
12 . The method of claim 11 , wherein the ECC decoding includes calculating error locate polynomials (ELPs) from the calculated syndromes.
13 . The method of claim 12 , wherein the ECC decoding includes deriving polynomial root values from the calculate ELPs.
14 . The method of claim 10 , wherein the random errors include at least one of bit and symbol errors.
15 . The method of claim 10 , wherein the plurality of memory components includes dynamic random access memory (DRAM) devices.
16 . The method of claim 15 , wherein the memory system is constructed in accordance compute express link (CXL) principles.
17 . The method of claim 16 , wherein the ECC decoding is performed in accordance with Reed Solomon (RS) codes.
18 . A non-transitory computer readable medium having stored thereon computer executable instructions that, if executed by a computing device, cause the computing device to perform a method for use by a memory controller of a memory system including a plurality of memory components, the method comprising:
receiving a data block and partitioning the data block into a plurality of memory segments distributed across the plurality of memory components;
constructing, via a plurality of memory components in communication with a controller, first and second codewords from a same set of data bits derived from the data block; and
performing error correction code (ECC) decoding on the first and second codewords that are received and read from the plurality of memory components;
wherein the ECC decoding is configured to:
(i) detect random errors in the first codeword using a first ECC decoding scheme, and
(ii) use corrected data bits from decoding the first codeword to correct erasures in the second codeword using a second ECC decoding scheme,
wherein the first and second codewords are associated by being derived from the same data block and are encoded using complementary ECC mechanisms that enable decoding of the second codeword using results from decoding the first codeword.
19 . The non-transitory computer readable medium of claim 18 , wherein the ECC decoding includes calculating error locate polynomials (ELPs) from the calculated syndromes.
20 . The non-transitory computer readable medium of claim 19 , wherein the ECC decoding includes deriving polynomial root values from the calculate ELPs.