COLLABORATIVE DECODING WITH ERASURE SEARCH TO RECOVER CORNER FAILS
Provided is a memory system comprising a plurality of memory components. The ECC decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ECC) decoding on the first and second codewords received read from the plurality of memory components wherein the ECC decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.
1 . A memory system comprising:
a plurality of memory components; and
a controller in communication with the plurality of memory components and configured to:
perform error correction code (ECC) decoding on first and second received codewords read from the plurality of memory components;
respectively calculate first and second syndromes for the first and second received codewords in parallel;
combine results of the first and second syndromes in a multiple shift register computation to generate a single error location polynomial;
produce a set of polynomial roots from the single error location polynomial;
determine whether each of the first and second codewords have non-zero syndrome values when the produced set of polynomial roots is invalid;
perform an erasure search (i) on symbols in only one the first and second codewords (ii) when only the first codeword or the second codeword has a non-zero syndrome value; and
correct each of the first and second codewords responsive to the performed erasure search.
2 . The memory system of claim 1 , wherein the erasure search is performed in accordance with Chien search principles.
3 . The memory system of claim 2 , wherein the search is performed on each of the symbols in the only one codeword in an iterative manner.
4 . The memory system of claim 3 , wherein the correcting further comprises validating roots of the identified error locations of the only one codeword.
5 . The memory system of claim 4 , wherein the roots are valid if only one search attempt was performed.
6 . The memory system of claim 5 , wherein error locations of the valid roots are identified.
7 . The memory system of claim 6 , further comprising calculating error magnitudes for each of the first and second codewords responsive to the error locations of the valid roots.
8 . A method comprising:
performing, via a plurality of memory components in communication with a controller, error correction code (ECC) decoding on first and second received codewords read from the plurality of memory components;
respectively calculating first and second syndromes for the first and second received codewords in parallel;
combining results of the first and second syndromes in a multiple shift register computation to generate a single error location polynomial;
producing a set of polynomial roots from the single error location polynomial;
determining whether each of the first and second codewords have non-zero syndrome values when the produced set of polynomial roots is invalid;
performing an erasure search (i) on symbols in only one the first and second codewords (ii) when only the first codeword or the second codeword has a non-zero syndrome value; and
correcting each of the first and second codewords responsive to the performed erasure search.
9 . The method of claim 8 , wherein the erasure search is performed in accordance with Chien search principles.
10 . The method of claim 9 , wherein the search is performed on each of the symbols in the only one codeword in an iterative manner.
11 . The method of claim 10 , wherein the correcting further comprises validating roots of the identified error locations of the only one codeword.
12 . The method of claim 11 , wherein the roots are valid if only one search attempt was performed.
13 . The method of claim 12 , wherein error locations of the valid roots are identified.
14 . The method of claim 13 , further comprising calculating error magnitudes for each of the first and second codewords responsive to the error locations of the valid roots.
15 . A non-transitory computer readable medium having stored thereon computer executable instructions that, if executed by a computing device, cause the computing device to perform a method for use by a memory controller of a memory system including a plurality of memory components, the method comprising:
performing, via a plurality of memory components in communication with a controller, error correction code (ECC) decoding on first and second received codewords read from the plurality of memory components;
respectively calculating first and second syndromes for the first and second received codewords in parallel;
combining results of the first and second syndromes in a multiple shift register computation to generate a single error location polynomial;
producing a set of polynomial roots from the single error location polynomial;
determining whether each of the first and second codewords have non-zero syndrome values when the produced set of polynomial roots is invalid;
performing an erasure search (i) on symbols in only one the first and second codewords (ii) when only the first codeword or the second codeword has a non-zero syndrome value; and
correcting each of the first and second codewords responsive to the performed erasure search.
16 . The method of claim 15 , wherein the erasure search is performed in accordance with Chien search principles.
17 . The method of claim 16 , wherein the search is performed on each of the symbols in the only one codeword in an iterative manner.
18 . The method of claim 17 , wherein the correcting further comprises validating roots of the identified error locations of the only one codeword.
19 . The method of claim 18 , wherein the roots are valid if only one search attempt was performed.
20 . The method of claim 19 , wherein error locations of the valid roots are identified.