IP Library › Granted Patent US 12,724,668
Granted Patent B2
US 12,724,668 · App. 18/421,444 · Granted Sep 1, 2026

Logical counters for a memory system

Inventor: Sai Krishna Mylavarapu (Folsom, CA)
Assignee: Micron Technology, Inc.
G06F11/1068G06F11/076G06F11/1435
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Quick Facts
Patent No.
US 12,724,668
App. No.
18/421,444
Granted
Sep 1, 2026
Kind
B2
Abstract

Methods, systems, and devices for logical counters for a memory system are described. A controller within a memory system may generate one or more logical counters that each correspond to a management counter of a memory die. The controller may store the logical counters at a logical address space associated with the memory system. The logical address space may correspond to a physical location within a memory array of the memory die. The controller may periodically read a value of a management counter and store the value to the logical counter. In some examples, if the memory system detects an error condition for the management counter, the memory system may perform a recovery operation for the data stored at the memory die.

Claims (62)

1 . A method, comprising:

generating, by a controller of a memory system, a logical counter associated with a management counter of a memory die of the memory system, wherein the logical counter stores, at a logical space associated with the memory die, a value indicating a quantity of access operations performed on the memory die of the memory system;

reading, by the controller, the value from the management counter based on generating the logical counter and in accordance with a duration, wherein the management counter tracks the quantity of access operations performed on the memory die of the memory system;

storing the value of the management counter to the logical counter based on reading the value from the management counter; and

transmitting, based on determining that the management counter satisfies an error condition, an indication of the error condition to a host system.

2 . The method of claim 1 , further comprising:

provisioning, by the controller, a subset of a plurality of physical addresses associated with the logical space, the subset of the plurality of physical addresses associated with the logical space for storing metadata associated with the memory die.

3 . The method of claim 2 , wherein the logical counter is associated with a subset of logical addresses corresponding to the subset of the plurality of physical addresses.

4 . The method of claim 1 , wherein the value is read from the management counter at a first time in accordance with the duration, the method further comprising:

determining, by the controller, that the duration has elapsed after the first time;

reading, by the controller, a second value from the management counter at a second time based on determining that the duration has elapsed; and

storing the second value of the management counter to the logical counter based on reading the second value from the management counter.

5 . The method of claim 4 , further comprising:

receiving a first command from the host system to update the duration to a second duration different than the duration; and

updating the duration to the second duration based on receiving the first command.

6 . The method of claim 1 , further comprising:

determining, by the controller, that the quantity of access operations performed on the memory die satisfies a threshold based on storing the value to the logical counter;

reading, by the controller, a third value from the management counter based on determining that the quantity of access operations performed on the memory die satisfies the threshold; and

storing the third value to the logical counter based on reading the third value from the management counter.

7 . The method of claim 6 , further comprising:

receiving a second command from the host system to update the threshold to a second threshold different than the threshold; and

updating the threshold to the second threshold based on receiving the second command.

8 . The method of claim 1 , further comprising:

determining, by the controller, that the management counter of the memory die satisfies the error condition based on storing the value to the logical counter; and

initiating a recovery operation for the memory die based on determining that the management counter satisfies the error condition.

9 . The method of claim 8 , further comprising:

reading, by the controller as part of the recovery operation, the value from the logical counter; and

transferring data from the memory die to a second memory die based on reading the value from the logical counter.

10 . The method of claim 8 , further comprising:

transmitting, by the controller as part of the recovery operation, the indication of the error condition to the host system based on determining that the management counter of the memory die satisfies the error condition.

11 . The method of claim 1 , further comprising:

generating, by the controller and based on reading the value from the management counter, one or more parity bits associated with the value; and

storing the one or more parity bits to one or more physical addresses associated with the logical space.

12 . The method of claim 1 , further comprising:

generating, by the controller, a second logical counter associated with a second management counter of a third memory die of the memory system;

reading, by the controller, a second value from the second management counter based on generating the second logical counter; and

storing the second value to one or more second physical addresses of the third memory die that are associated with the second logical counter based on reading the second value from the second management counter.

13 . The method of claim 1 , wherein the management counter comprises a wear leveling counter or a row hammer counter.

14 . A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to:

generate, by a controller of a memory system, a logical counter associated with a management counter of a memory die of the memory system, wherein the logical counter stores, at a logical space associated with the memory die, a value indicating a quantity of access operations performed on the memory die of the memory system;

read, by the controller, the value from the management counter based on generating the logical counter and in accordance with a duration, wherein the management counter tracks the quantity of access operations performed on the memory die of the memory system;

store the value of the management counter to the logical counter based on reading the value from the management counter; and

transmitting, based on determining that the management counter satisfies an error condition, an indication of the error condition to a host system.

15 . The non-transitory computer-readable medium of claim 14 , wherein the instructions are further executable by the processor to:

provision, by the controller, a subset of a plurality of physical addresses associated with the logical space, the subset of the plurality of physical addresses associated with the logical space for storing metadata associated with the memory die.

16 . The non-transitory computer-readable medium of claim 15 , wherein the logical counter is associated with a subset of logical addresses corresponding to the subset of the plurality of physical addresses.

17 . The non-transitory computer-readable medium of claim 14 , wherein the value is read from the management counter at a first time in accordance with the duration, and the instructions are further executable by the processor to:

determine, by the controller, that the duration has elapsed after the first time;

read, by the controller, a second value from the management counter at a second time based on determining that the duration has elapsed; and

store the second value of the management counter to the logical counter based on reading the second value from the management counter.

18 . The non-transitory computer-readable medium of claim 17 , wherein the instructions are further executable by the processor to:

receive a first command from the host system to update the duration to a second duration different than the duration; and

update the duration to the second duration based on receiving the first command.

19 . The non-transitory computer-readable medium of claim 14 , wherein the instructions are further executable by the processor to:

determine, by the controller, that the quantity of access operations performed on the memory die satisfies a threshold based on storing the value to the logical counter;

read, by the controller, a third value from the management counter based on determining that the quantity of access operations performed on the memory die satisfies the threshold; and

store the third value to the logical counter based on reading the third value from the management counter.

20 . An apparatus, comprising: one or more controllers associated with a memory device, wherein the one or more controllers are configured to cause the apparatus to:

generate, by a controller of a memory system, a logical counter associated with a management counter of a memory die of the memory system, wherein the logical counter stores, at a logical space associated with the memory die, a value indicating a quantity of access operations performed on the memory die of the memory system;

read, by the controller, the value from the management counter based on generating the logical counter and in accordance with a duration, wherein the management counter tracks the quantity of access operations performed on the memory die of the memory system;

store the value of the management counter to the logical counter based on reading the value from the management counter; and

transmitting, based on determining that the management counter satisfies an error condition, an indication of the error condition to a host system.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2025
From: MYLAVARAPU, SAI KRISHNA
To: MICRON TECHNOLOGY, INC.
Reel/Frame 072088/0533 →
Continuity (2)
Provisional Application 63443852 · Feb 7, 2023
Related Publication 20240264904A1 · Aug 8, 2024
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