Granted Patent B2

US 12,363,043 · App. 18/422,113 · Granted Jul 15, 2025

Inventors: Sujeet Shyamsundar Mate (Tampere, FI); Kashyap Kammachi Sreedhar (Tampere, FI); Igor Danilo Diego Curcio (Tampere, FI); Serhan Gul (Berlin, DE); Lauri Aleksi Ilola (Tampere, FI); Saba Ahsan (Espoo, FI)

Assignee: Nokia Technologies Oy

H04L47/24H04L65/65

Abstract

Claims (53)

1. An apparatus comprising:

at least one processor; and

at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to:

receive, from a first user equipment, at least one real-time transport protocol header extension configured to handle at least one protocol data unit, wherein the at least one real-time transport protocol header extension comprises, at least, one or more application controlled bits;

determine whether the one or more application controlled bits are valid; and

set values for one or more network controlled bits of the at least one real-time transport protocol header extension based, at least partially, on a determination of whether the one or more application controlled bits are valid, wherein the one or more application controlled bits comprise bits that do not overlap with the one or more network controlled bits.

2. The apparatus of claim 1 , wherein the one or more network controlled bits comprise at least one of:

an indication of validation performed or not performed,

an indication of whether the one or more application controlled bits are valid or invalid,

an indication of protocol data unit handling priority determined with a network element,

an indication of a network congestion status, or

an indication of a network action.

3. The apparatus of claim 1 , wherein the at least one memory stores instructions that, when executed by the at least one processor, cause the apparatus to:

transmit, to a second user equipment, the at least one real-time transport protocol header extension.

4. The apparatus of claim 1 , wherein the at least one memory stores instructions that, when executed by the at least one processor, cause the apparatus to:

perform protocol data unit handling prioritization based on the one or more application controlled bits in response to a determination that the one or more application controlled bits are valid.

5. The apparatus of claim 1 , wherein the at least one memory stores instructions that, when executed by the at least one processor, cause the apparatus to:

perform protocol data unit handling prioritization based on the one or more network controlled bits in response to a determination that the one or more application controlled bits are invalid.

6. The apparatus of claim 1 , wherein the at least one memory stores instructions that, when executed by the at least one processor, cause the apparatus to:

discard the at least one protocol data unit in response to a determination that the one or more application controlled bits are invalid.

7. The apparatus of claim 1 , wherein the at least one memory stores instructions that, when executed by the at least one processor, cause the apparatus to:

forward the at least one protocol data unit in response to a determination that the one or more application controlled bits are invalid.

8. The apparatus of claim 1 , wherein the values for the one or more network controlled bits are configured to indicate that the one or more application controlled bits are invalid.

9. The apparatus of claim 1 , wherein the at least one memory stores instructions that, when executed by the at least one processor, cause the apparatus to:

determine that the one or more application controlled bits are valid;

determine to at least one of:

drop transmission of the at least one protocol data unit, or

delay the transmission of the at least one protocol data unit; and

cause transmission, to the first user equipment, of an indication of dropping or delaying the transmission of the at least one protocol data unit.

10. The apparatus of claim 1 , wherein the at least one memory stores instructions that, when executed by the at least one processor, cause the apparatus to:

determine that at least one of the one or more application controlled bits are invalid; and

rewrite the at least one application controlled bit.

11. The apparatus of claim 1 , wherein the at least one memory stores instructions that, when executed by the at least one processor, cause the apparatus to:

transmit, to a second user equipment, the one or more application controlled bits and the one or more network controlled bits without the at least one protocol data unit.

12. A method comprising:

receiving, from a first user equipment, at least one real-time transport protocol header extension configured to handle at least one protocol data unit, wherein the at least one real-time transport protocol header extension comprises, at least, one or more application controlled bits;

determining whether the one or more application controlled bits are valid; and

setting values for one or more network controlled bits of the at least one real-time transport protocol header extension based, at least partially, on a determination of whether the one or more application controlled bits are valid, wherein the one or more application controlled bits comprise bits that do not overlap with the one or more network controlled bits.

13. An apparatus comprising:

at least one processor; and

at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to:

receive, from a first user equipment, at least one real-time transport protocol header extension configured to handle at least one protocol data unit, wherein the at least one real-time transport protocol header extension comprises, at least, one or more application controlled bits and one or more network controlled bits, wherein the one or more application controlled bits comprise bits that do not overlap with the one or more network controlled bits;

determine whether the one or more application controlled bits are valid;

in response to a determination that the one or more application controlled bits are valid, transmit the at least one protocol data unit to a second user equipment based, at least partially, on the one or more application controlled bits; and

in response to a determination that the one or more application controlled bits are invalid, transmit the at least one protocol data unit to a second user equipment based, at least partially, on the one or more network controlled bits.

14. The apparatus of claim 13 , wherein the one or more network controlled bits comprise at least one of:

an indication of validation performed or not performed,

an indication of whether the one or more application controlled bits are valid or invalid,

an indication of protocol data unit handling priority determined with a network element,

an indication of a network congestion status, or

an indication of a network action.

15. The apparatus of claim 13 , wherein the at least one memory stores instructions that, when executed by the at least one processor, cause the apparatus to:

determine that the one or more application controlled bits are invalid based, at least partially, on the one or more network controlled bits.

Assignments (3)

Continuity (2)

References Cited (17)

Cited By (4)

US 12,512,927 US 12,513,227 US 12,517,791 US 12,574,449