Shadow cache for securing conditional speculative instruction execution
View Patent ↗A computing device, having: a processor; memory; a first cache coupled between the memory and the processor; and a second cache coupled between the memory and the processor. During speculative execution of one or more instructions, effects of the speculative execution are contained within the second cache.
1 . A computing device, comprising:
a processor;
a first cache; and
a second cache;
wherein the processor is configured to:
determine presence of two branches of second instructions following a first branch instruction, the two branches including a first branch and a second branch;
execute the first branch using the first cache; and
execute the second branch using the second cache.
2 . The computing device of claim 1 , further comprising:
a memory;
wherein the first cache and the second cache are configured for the processor to access the memory.
3 . The computing device of claim 2 , wherein the first branch and the second branch are executed using the first cache and the second cache respectively during speculative execution.
4 . The computing device of claim 2 , wherein execution of the first branch instruction is configured to select one of the two branches for execution based on a condition; and the first branch and the second branch are executed using the first cache and the second cache respectively before a result of evaluation of the condition is available to the processor.
5 . The computing device of claim 2 , wherein the first branch instruction includes a call to a routine corresponding to the second branch.
6 . The computing device of claim 5 , wherein the processor is further configured to inspect a memory address associated with the second branch to determine whether to execute the second branch.
7 . The computing device of claim 5 , wherein the processor is further configured to determine whether to execute the second branch on speculation based on an object identifier embedded in a memory address associated with the second branch.
8 . A method, comprising:
coupling a cache system between a processor and a memory; and
coupling a shadow cache between the processor and the memory in parallel with the cache system, wherein a location in the memory is accessible to the processor via both the cache system and the shadow cache.
9 . The method of claim 8 , wherein the cache system includes a level two cache.
10 . The method of claim 9 , wherein the cache system further includes a level three cache connected to the level two cache in series between the processor and the memory.
11 . The method of claim 10 , wherein a level one cache is further connected in series to the level two cache.
12 . The method of claim 11 , further comprising:
accessing, by the processor, the memory via the cache system during normal execution of instructions; and
accessing, by the processor, the memory via the shadow cache during speculative execution of instructions.
13 . The method of claim 12 , further comprising:
initializing the shadow cache according to memory states cached in the cache system prior to the speculative execution.
14 . The method of claim 12 , further comprising:
mirroring, in the shadow cache, memory states cached in the cache system during the normal execution.
15 . A system, comprising:
a cache system configured between a processor and a memory; and
a shadow cache configured between the processor and the memory in parallel with the cache system, wherein a location in the memory is accessible to the processor via both the cache system and the shadow cache.
16 . The system of claim 15 , wherein the first cache system and the shadow cache have a same number of cache levels.
17 . The system of claim 15 , wherein the first cache system and the shadow cache have different numbers of cache levels.
18 . The system of claim 15 , wherein the shadow cache is configured to mirror the cache system during a first type of operations of the processor; and the shadow cache is configured to be used to access the memory during a second type of operations of the processor without using the cache system.
19 . The system of claim 18 , wherein the first type of operations is associated with normal execution of instructions in the processor; and the second type of operations is associated with speculative execution of instructions in the processor.
20 . The system of claim 18 , wherein during the second type of operations, the processor is blocked from changing memory states cached in the cache system and blocked from changing states in the memory.