IP Library › Granted Patent US 12,474,844
Granted Patent B2
US 12,474,844 · App. 18/425,725 · Granted Nov 18, 2025

Memory array accessibility

Inventors: Daniel B. Penney (Wylie, TX); Gary L. Howe (Plano, TX)
G06F3/0622G06F3/0644G06F3/0659G06F3/0683G11C7/065G11C7/1006
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Quick Facts
Patent No.
US 12,474,844
App. No.
18/425,725
Granted
Nov 18, 2025
Kind
B2
Abstract

Apparatuses and methods for memory array accessibility can include an apparatus with an array of memory cells. The array can include a first portion accessible by a controller of the array and inaccessible to devices external to the apparatus. The array can include a second portion accessible to the devices external to the apparatus. The array can include a number of registers that store row address that indicate which portion of the array is the first portion. The apparatus can include the controller configured to access the number of registers to allow access to the second portion by the devices external to the apparatus based on the stored row addresses.

Claims (41)

1 . An apparatus, comprising:

an array of memory cells, comprising:

a first portion of memory cells configured to store data; and

a second portion of memory cells configured to store instructions for executing processing-in-memory (PIM) instructions on the data stored in the first portion of memory cells; and

a controller configured to execute the PIM instructions stored in the second portion of memory cells on the data stored in the first portion of memory cells.

2 . The apparatus of claim 1 , wherein the array includes a number of registers that are mapped to addresses in the second portion of memory cells.

3 . The apparatus of claim 1 , wherein:

the first portion of memory cells includes a number of rows of memory cells; and

the second portion of memory cells includes a number of rows of memory cells;

wherein an initial row of the number of rows of memory cells of the first portion is adjacent an ending row of the number of rows of memory cells of the second portion.

4 . The apparatus of claim 1 , wherein array of memory cells comprises a bank of dynamic random access memory (DRAM) cells.

5 . The apparatus of claim 1 , wherein the PIM instructions comprise instructions for performing bit-vector operations on the data stored in the first portion of memory cells.

6 . The apparatus of claim 5 , wherein the bit-vector operations include logical operations.

7 . The apparatus of claim 5 , wherein the bit-vector operations include mathematical operations.

8 . A method, comprising:

accessing data stored in a first portion of memory cells of an array of memory cells; and

executing processing-in-memory (PIM) instructions stored in a second portion of memory cells of the array of memory cells on the data accessed from the first portion of memory cells.

9 . The method of claim 8 , wherein accessing the data stored in the first portion of memory cells of the array comprises accessing data stored in a single row of the first portion of memory cells of the array.

10 . The method of claim 8 , wherein executing the PIM instructions on the data accessed from the first portion of memory cells comprises using the accessed data as an operand in a bit-vector operation.

11 . The method of claim 8 , wherein accessing the data stored in the first portion of memory cells of the array comprises sensing the data stored in the first portion of memory cells of the array.

12 . The method of claim 8 , wherein the method includes programming data to the first portion of memory cells of the array.

13 . The method of claim 8 , wherein the method includes storing a result of the executed PIM instructions in the second portion of memory cells of the array.

14 . An apparatus, comprising:

a plurality of arrays of memory cells, wherein each of the plurality of arrays includes:

a first portion of memory cells configured to store data;

a second portion of memory cells configured to store instructions for executing processing-in-memory (PIM) instructions on the data stored in the first portion of memory cells; and

a number of registers that are mapped to addresses in the second portion of memory cells.

15 . The apparatus of claim 14 , wherein the apparatus includes a controller configured to:

access the data stored in the first portion of memory cells of the plurality of arrays; and

execute the PIM instructions stored in the second portion of memory cells of the plurality of arrays on the accessed data.

16 . The apparatus of claim 15 , wherein the controller is configured to read the addresses in the second portion of memory cells to which the number of registers are mapped.

17 . The apparatus of claim 14 , wherein the number of registers of each respective one of the plurality of arrays includes:

a first register that is mapped to a first address in the second portion of memory cells of that respective one of the plurality of arrays; and

a second register that is mapped to a second address in the second portion of memory cells of that respective one of the plurality of arrays.

18 . The apparatus of claim 17 , wherein:

the first address is an address of a first row in the second portion of memory cells of that respective one of the plurality of arrays; and

the second address is an address of a second row in the second portion of memory cells of that respective one of the plurality of arrays.

19 . The apparatus of claim 18 , wherein:

the first row is an initial row in the second portion of memory cells of that respective one of the plurality of arrays; and

the second row is an ending row in the second portion of memory cells of that respective one of the plurality of arrays.

20 . The apparatus of claim 14 , wherein the number of registers of each respective one of the plurality of arrays are included in a periphery of that respective array.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 28, 2024
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP LLC
Reel/Frame 066592/0828 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2024
From: PENNEY, DANIEL B.; HOWE, GARY L.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 066535/0721 →
Continuity (4)
Continuation 17531573 · Nov 19, 2021
Division 16555293 · Aug 29, 2019
Continuation 15691484 · Aug 30, 2017
Related Publication 20240168656A1 · May 23, 2024
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