Independently addressable memory array address spaces
Examples of the present disclosure provide devices and methods for accessing a memory array address space. An example memory array comprising a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines and a second address space comprising memory cells coupled to a second number of select lines and to the number of sense lines. The first address space is independently addressable relative to the second address space.
1. A memory array, comprising:
a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines; and
a second address space comprising memory cells coupled to a second number of select lines and to the number of sense lines;
wherein the first address space is independently addressable relative to the second address space; and
wherein the first number of select lines are coupled to a decoder and the second number of select lines are not coupled to the decoder and are coupled directly to an address circuitry.
2. The memory array of claim 1 , wherein only one of the first number of select lines is activated at a given time and wherein the second number of select lines are activated simultaneously.
3. The memory array of claim 2 , wherein a select line of the first number of select lines and a select line of the second number of select lines are activated simultaneously.
4. The memory array of claim 1 , wherein a select line of the first number of select lines and a select line of the second number of select lines are activated simultaneously.
5. The memory array of claim 4 , wherein the select line of the first number of select lines and all of the second number of select lines are activated simultaneously.
6. The memory array of claim 4 , wherein only one of the first number of select lines is activated at a given time.
7. The memory array of claim 1 , wherein the first address space being independently addressable relative to the second address space comprises the first number of select lines being coupled to the decoder and the second number of select lines being coupled directly to address circuitry.
8. The memory array of claim 7 , wherein the address circuitry is coupled to the decoder.
9. The memory array of claim 1 , wherein the first address space being independently addressable relative to the second address space comprises the first number of select lines being coupled to a number of shared address lines via the decoder and the second number of select lines being discreetly addressable.
10. The memory array of claim 1 , wherein each of the second number of select lines are individually addressed.
11. The memory array of claim 1 , wherein the memory cells that comprise the first address space are coupled to the memory cells that comprise the second address space through the number of sense lines.
12. The memory array of claim 1 , wherein the first number of select lines are decoded independently of the second number of select lines.
13. The memory array of claim 1 , wherein the memory cells that comprise the second address space are on an edge portion of the memory array.
14. The memory array of claim 1 , wherein the second address space is used as temporary storage for a compute component.
15. The memory array of claim 14 , wherein the temporary storage is used as a register by the compute component.
16. The memory array of claim 14 , wherein the compute component is coupled to the number of sense lines and comprises transistors formed on pitch with the memory cells.
17. A method comprising:
activating a select line of a first number of select lines of a memory array;
sensing, via sensing circuitry coupled to sense lines of the memory array, data stored in a first number of memory cells coupled to the select line; and
copying the data stored in the first number of memory cells coupled to the select line of the first number of select lines to a second number of memory cells coupled to a select line of a second number of select lines of the memory array;
wherein the first number of select lines are independently addressable relative to the second number of select lines; and
wherein the first number of select lines are coupled to a decoder and the second number of select lines are not coupled to the decoder and are coupled directly to an address circuitry.
18. The method of claim 17 , wherein copying the data stored in the first number of memory cells includes copying the data from the sensing circuitry to the second number of memory cells without accessing an input/output (I/O) line.
19. The method of claim 18 , wherein copying the data from the sensing circuitry to the second number of memory cells further includes copying the data from the sensing circuitry to a third number of memory cells coupled to another select line of the first number of select lines.
20. The method of claim 19 , wherein copying the data from the sensing circuitry to the second number of memory cells and copying the data from the sensing circuitry to the third number of memory cells occurs simultaneously.
21. The method of claim 17 , wherein activating the select line of the first number of select lines includes activating the select line via decode circuitry that is independent of decode circuitry associated with activating the select line of the second number of select lines.
22. A method comprising:
activating a select line of a first number of select lines of a memory array, wherein memory cells coupled to the first number of select lines are used as temporary storage by a compute component;
sensing, via sensing circuitry coupled to sense lines of the memory array, data stored in a first number of memory cells coupled to the select line of the first number of select lines; and
copying the data stored in the first number of memory cells to a second number of memory cells coupled to a select line of a second number of select lines of the memory array;
wherein the first number of select lines are independently addressable relative to the second number of select lines; and
wherein the first number of select lines are coupled to a decoder and the second number of select lines are not coupled to the decoder and are coupled directly to an address circuitry.
23. The method of claim 22 , wherein copying the data stored in the first number of memory cells includes copying the data from the first number of memory cells that are used as temporary storage to the sensing circuitry.
24. The method of claim 23 , wherein copying the data stored in the first number of memory cells includes copying the data from the sensing circuitry to the second number of memory cells without accessing an input/output (I/O) line.
25. The method of claim 23 , wherein copying the data stored in the first number of memory cells includes copying the data from the sensing circuitry to a third number of memory cells coupled to another select line of the first number of select lines.
26. The method of claim 23 , wherein copying the data stored in the first number of memory cells includes copying the data from the sensing circuitry to a third number of memory cells coupled to another select line of the first number of select lines and the first number of memory cells coupled to the select line of the first umber of select lines simultaneously.
27. The method of claim 22 , wherein copying the data stored in the first number of memory cells includes copying within a single sensing cycle.