Hardware and software hybrid configuration of DRAM channel interleaving management
Various embodiments include a memory controller and methods for implementing functions of the memory controller for hardware and software hybrid configuration of memory channel interleaving management. Embodiments may include a memory controller having a signaling mechanism configured to provide a configuration signal for indicating to the memory controller a layer of a memory channel interleaving hierarchy for software memory channel interleaving management, a processor configured to read the configuration signal and select the layer of the memory channel interleaving hierarchy for software memory channel interleaving management based on the configuration signal, and an integrated circuit configured to implement memory channel interleaving according to a layer of the memory channel interleaving hierarchy for hardware memory channel interleaving management. In some embodiments, the layers for software or hardware memory channel interleaving management may include any of an intra-memory channel group, an inter-memory channel group, or an inter-die memory channel group layer.
1 . A memory subsystem for a computing device, comprising:
at least one memory controller comprising:
at least one signaling mechanism configured to provide at least one configuration signal for indicating to the memory controller at least one layer of a memory channel interleaving hierarchy for software memory channel interleaving management;
at least one processor configured to:
read the at least one configuration signal;
select the at least one layer of the memory channel interleaving hierarchy for software memory channel interleaving management based on the at least one configuration signal; and
load at least one memory map corresponding to the at least one layer of the memory channel interleaving hierarchy for software memory channel interleaving management, wherein the at least one memory map is configured to present a view of memory of the memory subsystem; and
at least one integrated circuit configured to implement memory channel interleaving according to at least one layer of the memory channel interleaving hierarchy for hardware memory channel interleaving management concurrently with software memory channel interleaving management by the at least one processor.
2 . The memory subsystem of claim 1 , wherein:
the at least one layer of the memory channel interleaving hierarchy for software memory channel interleaving management comprises at least one of an intra-memory channel group layer, an inter-memory channel group layer, or an inter-die memory channel group layer; and
the at least one layer of the memory channel interleaving hierarchy for hardware memory channel interleaving management comprises at least one of the intra-memory channel group layer, the inter-memory channel group layer, or the inter-die memory channel group layer that is different from the at least one layer of the memory channel interleaving hierarchy for software memory channel interleaving management.
3 . The memory subsystem of claim 1 , wherein the at least one processor is further configured to implement memory channel interleaving according to the at least one layer of the memory channel interleaving hierarchy for software memory channel interleaving management.
4 . The memory subsystem of claim 1 , wherein:
the at least one processor is further configured to implement the memory channel interleaving across a plurality of memory channels of at least one memory channel group of the at least one layer of the memory channel interleaving hierarchy for software memory channel interleaving management; and
the at least one integrated circuit is further configured to implement the memory channel interleaving across a plurality of memory channels of at least one memory channel group of the at least one layer of the memory channel interleaving hierarchy for hardware memory channel interleaving management.
5 . The memory subsystem of claim 1 , wherein:
the at least one configuration signal is further configured to indicate to the memory controller the at least one layer of the memory channel interleaving hierarchy for hardware memory channel interleaving management; and
the at least one processor is further configured to select the at least one integrated circuit configured to implement memory channel interleaving according to the at least one layer of the memory channel interleaving hierarchy for hardware memory channel interleaving management based on the at least one configuration signal.
6 . The memory subsystem of claim 1 , wherein the least one signaling mechanism comprises at least one of a register, an electronic fuse, or a pin.
7 . A method for configuration of memory channel interleaving management implemented by a memory controller, comprising:
reading at least one configuration signal for indicating to the memory controller at least one layer of a memory channel interleaving hierarchy for software memory channel interleaving management;
selecting the at least one layer of the memory channel interleaving hierarchy for software memory channel interleaving management based on the at least one configuration signal;
implementing, by at least one integrated circuit, memory channel interleaving according to at least one layer of the memory channel interleaving hierarchy for hardware memory channel interleaving management concurrently with software memory channel interleaving management by the memory controller; and
loading at least one memory map corresponding to the at least one layer of the memory channel interleaving hierarchy for software memory channel interleaving management, wherein the at least one memory map is configured to present a view of memory of the memory subsystem.
8 . The method of claim 7 , wherein:
the at least one layer of the memory channel interleaving hierarchy for software memory channel interleaving management comprises at least one of an intra-memory channel group layer, an inter-memory channel group layer, or an inter-die memory channel group layer; and
the at least one layer of the memory channel interleaving hierarchy for hardware memory channel interleaving management comprises at least one of the intra-memory channel group layer, the inter-memory channel group layer, or the inter-die memory channel group layer that is different from the at least one layer of the memory channel interleaving hierarchy for software memory channel interleaving management.
9 . The method of claim 7 , further comprising implementing memory channel interleaving according to the at least one layer of the memory channel interleaving hierarchy for software memory channel interleaving management.
10 . The method of claim 7 , wherein implementing, by the at least one integrated circuit, the memory channel interleaving according to the at least one layer of the memory channel interleaving hierarchy for hardware memory channel interleaving management comprises implementing the memory channel interleaving across a plurality of memory channels of at least one memory channel group of the at least one layer of the memory channel interleaving hierarchy for hardware memory channel interleaving management,
the method further comprising implementing the memory channel interleaving across a plurality of memory channels of at least one memory channel group of the at least one layer of the memory channel interleaving hierarchy for software memory channel interleaving management.
11 . The method of claim 7 , wherein the at least one configuration signal is further configured to indicate to the memory controller the at least one layer of the memory channel interleaving hierarchy for hardware memory channel interleaving management,
the method further comprising selecting the at least one integrated circuit configured to implement memory channel interleaving according to the at least one layer of the memory channel interleaving hierarchy for hardware memory channel interleaving management based on the at least one configuration signal.
12 . The method of claim 7 , wherein the least one signaling mechanism comprises at least one of a register, an electronic fuse, or a pin.
13 . A computing device, comprising:
means for reading at least one configuration signal for indicating at least one layer of a memory channel interleaving hierarchy for software memory channel interleaving management;
means for selecting the at least one layer of the memory channel interleaving hierarchy for software memory channel interleaving management based on the at least one configuration signal;
means for implementing memory channel interleaving according to at least one layer of the memory channel interleaving hierarchy for hardware memory channel interleaving management concurrently with means for implementing software memory channel interleaving management; and
means for loading at least one memory map corresponding to the at least one layer of the memory channel interleaving hierarchy for software memory channel interleaving management, wherein the at least one memory map is configured to present a view of memory of the memory subsystem.
14 . The computing device of claim 13 , wherein:
the at least one layer of the memory channel interleaving hierarchy for software memory channel interleaving management comprises at least one of an intra-memory channel group layer, an inter-memory channel group layer, or an inter-die memory channel group layer; and
the at least one layer of the memory channel interleaving hierarchy for hardware memory channel interleaving management comprises at least one of the intra-memory channel group layer, the inter-memory channel group layer, or the inter-die memory channel group layer that is different from the at least one layer of the memory channel interleaving hierarchy for software memory channel interleaving management.
15 . The computing device of claim 13 , wherein means for implementing software memory channel interleaving management comprises means for implementing memory channel interleaving according to the at least one layer of the memory channel interleaving hierarchy for software memory channel interleaving management.
16 . The computing device of claim 13 , wherein:
means for implementing the memory channel interleaving according to the at least one layer of the memory channel interleaving hierarchy for hardware memory channel interleaving management comprises means for implementing the memory channel interleaving across a plurality of memory channels of at least one memory channel group of the at least one layer of the memory channel interleaving hierarchy for hardware memory channel interleaving management; and
wherein means for implementing software memory channel interleaving management comprises means for implementing the memory channel interleaving across a plurality of memory channels of at least one memory channel group of the at least one layer of the memory channel interleaving hierarchy for software memory channel interleaving management.
17 . The computing device of claim 13 , wherein the at least one configuration signal is further configured to indicate the at least one layer of the memory channel interleaving hierarchy for hardware memory channel interleaving management,
the computing device further comprising means for selecting the means for implementing memory channel interleaving according to the at least one layer of the memory channel interleaving hierarchy for hardware memory channel interleaving management based on the at least one configuration signal.