IP Library Granted Patent US 9,092,327
Granted Patent B2
US 9,092,327 · App. 13/781,366 · Granted Jul 28, 2015

System and method for allocating memory to dissimilar memory devices using quality of service

Inventors: Subrato K. De (San Diego, CA); Richard A. Stewart (San Diego, CA); Gheorghe Calin Cascaval (San Diego, CA); Dexter T. Chun (San Diego, CA)
Assignee: QUALCOMM Incorporated
G06F12/0607G06F12/0638G11C7/1072
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,092,327
App. No.
13/781,366
Granted
Jul 28, 2015
Kind
B2
Abstract

Systems and methods are provided for allocating memory to dissimilar memory devices. An exemplary embodiment includes a method for allocating memory to dissimilar memory devices. An interleave bandwidth ratio is determined, which comprises a ratio of bandwidths for two or more dissimilar memory devices. The dissimilar memory devices are interleaved according to the interleave bandwidth ratio to define two or more memory zones having different performance levels. Memory address requests are allocated to the memory zones based on a quality of service (QoS).

Claims (41)

1. A method for allocating memory to dissimilar memory devices, the method comprising:

determining an interleave bandwidth ratio comprising a ratio of bandwidths for two or more dissimilar memory devices;

interleaving the dissimilar memory devices according to the interleave bandwidth ratio and defining two or more memory zones having different performance levels; and

allocating memory address requests to the memory zones based on a quality of service (QoS).

2. The method of claim 1 , wherein the dissimilar memory devices comprise a first type of dynamic random access memory (DRAM) and a second type of DRAM.

3. The method of claim 2 , wherein one or more of the first type or second type of DRAM comprises a double data rate (DDR) memory.

4. The method of claim 1 , wherein the QoS comprises a declared QoS from an application.

5. The method of claim 4 , wherein the allocating the memory address requests to the memory zones based on the QoS comprises a high-level operating system (HLOS) receiving the memory address requests.

6. The method of claim 1 , wherein the QoS is declared via an application program interface (API) associated with a high-level operating system (HLOS).

7. The method of claim 1 , wherein the QoS comprises an estimated QoS based on a current performance of one or more of the memory zones.

8. The method of claim 1 , wherein the allocating memory address requests to the memory zones based on the quality of service (QoS) comprises a memory channel optimization module estimating the QoS.

9. A system for allocating memory to dissimilar memory devices, the system comprising:

means for determining an interleave bandwidth ratio comprising a ratio of bandwidths for two or more dissimilar memory devices;

means for interleaving the dissimilar memory devices according to the interleave bandwidth ratio and defining two or more memory zones having different performance levels; and

means for allocating memory address requests to the memory zones based on a quality of service (QoS);

wherein the means for determining the interleave bandwidth ratio, means for interleaving the dissimilar memory devices, and means for allocating memory address requests to the memory zones comprise hardware.

10. The system of claim 9 , wherein the dissimilar memory devices comprise a first type of dynamic random access memory (DRAM) and a second type of DRAM.

11. The system of claim 10 , wherein one or more of the first type or second type of DRAM comprises a double data rate (DDR) memory.

12. The system of claim 9 , wherein the QoS comprises one of a declared QoS from an application or an estimated QoS.

13. The system of claim 9 , wherein the means for allocating comprises one of a high-level operating system (HLOS) and memory channel optimization module.

14. A memory system for managing memory devices in a computer system, the memory system comprising:

a first type of memory device;

a second type of memory device;

a memory channel optimization module in communication with the first and second types of memory devices, the memory channel optimization module operable in a unified mode of operation to interleave the first and second types of memory devices by:

determining an interleave bandwidth ratio comprising a ratio of bandwidths for the first type of memory device and the second type of memory device; and

interleaving the first and second types of memory devices according to the interleave bandwidth ratio and defining two or more memory zones having different performance levels; and

a high-level operating system (HLOS) in communication with the memory channel optimization module for allocating memory address requests from one or more applications to one of the memory zones based on a QoS.

15. The memory system of claim 14 , wherein the first type of memory device comprises a first type of double data rate (DDR) memory and the second type of memory device comprises a second type of DDR memory.

16. The memory system of claim 14 , wherein the HLOS receives the QoS via an associated application program interface (API).

17. The memory system of claim 14 , wherein the memory channel optimization module is further operable to estimate the QoS based on a current performance level for one or more of the memory zones.

18. A computer program product comprising a non-transitory computer usable medium having a computer readable program code embodied therein, the computer readable program code adapted to be executed to implement a method for dynamically allocating memory to dissimilar memory devices, the method comprising:

determining an interleave bandwidth ratio comprising a ratio of bandwidths for two or more dissimilar memory devices;

interleaving the dissimilar memory devices according to the interleave bandwidth ratio and defining two or more memory zones having different performance levels; and

allocating memory address requests to the memory zones based on a quality of service (QoS).

19. The computer program product of claim 18 , wherein the dissimilar memory devices comprise a first type of dynamic random access memory (DRAM) and a second type of DRAM.

20. The computer program product of claim 19 , wherein one or more of the first type or second type of DRAM comprises a double data rate (DDR) memory.

21. The computer program product of claim 18 , wherein the QoS comprises a declared QoS from an application.

22. The computer program product of claim 21 , wherein the allocating the memory address requests to the memory zones based on the declared QoS comprises a high-level operating system (HLOS) receiving the memory address requests.

23. The computer program product of claim 18 , wherein the QoS is declared via an application program interface (API) associated with a high-level operating system (HLOS).

24. The computer program product of claim 18 , wherein the QoS comprises an estimated QoS based on a current performance of one or more of the memory zones.

25. The computer program product of claim 18 , wherein the allocating memory address requests to the memory zones based on the quality of service (QoS) comprises a memory channel optimization module estimating the QoS.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 30, 2015
From: DE, SUBRATO K.; STEWART, RICHARD A.; CASCAVAL, GEORGE CALIN; CHUN, DEXTER T.
To: QUALCOMM INCORPORATED
Reel/Frame 036925/0720 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2013
From: DE, SUBRATO K.; STEWART, RICHARD A.; CASCAVAL, GHEORGHE CALIN; CHUN, DEXTER T.
To: QUALCOMM INCORPORATED
Reel/Frame 030224/0165 →
Continuity (3)
Continuation In Part 13726537 · Dec 24, 2012
Provisional Application 61735352 · Dec 10, 2012
Related Publication 20140164690A1 · Jun 12, 2014