Leakage compensation circuit for content addressable memory (CAM) cell

1 . A leakage compensation content addressable memory (CAM) circuit, comprising:

at least one CAM cell configured to store a bit value, wherein the CAM cell comprises a first CAM cell transistor and a fourth CAM cell transistor that are first type transistors and a second CAM cell transistor, a third CAM cell transistor, a fifth CAM cell transistor and a sixth CAM cell transistor that are second type transistors;

at least one compensation CAM cell configured to store the bit value of the CAM cell and to cancel leakage current of the CAM cell, wherein the compensation CAM cell comprises a first compensation CAM cell transistor and a fourth compensation CAM cell transistor that are second type transistors and a second compensation CAM cell transistor, a third compensation CAM cell transistor, a fifth compensation CAM cell transistor and a sixth compensation CAM cell transistor that are first type transistors;

one or more bit line drivers configured to supply output to bit lines of the CAM cell and the compensation CAM cell; and

one or more word line drivers configured to supply output to word lines of the CAM cell and the compensation CAM cell.

2 . The leakage compensation CAM circuit of claim 1 wherein the first type transistor is a p-channel field effect transistor (PFET) and the second type transistor is an n-channel field effect transistor (NFET), or wherein the first type transistor is the NFET and the second type transistor is the PFET.

3 . The leakage compensation CAM circuit of claim 1 wherein the one or more bit line drivers comprises:

at least one main bit line driver coupled to the bit lines of the CAM cell to supply output to the CAM cell; and

at least one compensation bit line driver coupled to the bit lines of the compensation CAM cell to supply output to the compensation CAM cell.

4 . The leakage compensation CAM circuit of claim 1 wherein the bit lines of the CAM cell comprise a first bit line, a second bit line, a third bit line and a fourth bit line, and wherein:

a gate of the second CAM cell transistor is coupled to a first word line, and a source of the second CAM cell transistor is coupled to the first bit line of the CAM cell;

a gate of the third CAM cell transistor is coupled to a second word line, and a source of the third CAM cell transistor is coupled to the second bit line of the CAM cell,

a gate of the fourth CAM cell transistor is coupled to drains of the first, second and third CAM cell transistors of the CAM cell;

a gate of the fifth CAM cell transistor is coupled to the first word line, and a source of the fifth CAM cell transistor is coupled to the third bit line of the CAM cell; and

a gate of the sixth CAM cell transistor is coupled to the second word line and a source of the sixth CAM cell transistor is coupled to the fourth bit line of the CAM cell, and wherein a gate of the first CAM cell transistor is coupled to drains of the fourth, fifth and sixth CAM cell transistors of the CAM cell.

5 . The leakage compensation CAM circuit of claim 4 wherein the bit lines of the compensation CAM cell comprise a first bit line, a second bit line, a third bit line and a fourth bit line, and wherein:

a gate of the second compensation CAM cell transistor is coupled to a third word line, and a source of the second compensation CAM cell transistor is coupled to the first bit line of the compensation CAM cell;

a gate of the third compensation CAM cell transistor is coupled to a fourth word line, and a source of the third compensation CAM cell transistor is coupled to the second bit line of the compensation CAM cell;

a gate of the fourth compensation CAM cell transistor is coupled to drains of the first, second and third compensation CAM cell transistors;

a gate of the fifth compensation CAM cell transistor is coupled to the third word line, and a source of the fifth compensation CAM cell transistor is coupled to the third bit line of the compensation CAM cell; and

a gate of the sixth compensation CAM cell transistor is coupled to the fourth word line and a source of the sixth compensation CAM cell transistor is coupled to the fourth bit line of the compensation CAM cell, and wherein a gate of the first compensation CAM cell transistor is coupled to drains of the fourth, fifth and sixth compensation CAM cell transistors.

6 . The leakage compensation CAM circuit of claim 5 wherein the first and fourth bit lines of the CAM cell are combined into a single line, the second and third bit lines of the CAM cell are combined into a single line, the first and fourth bit lines of the compensation CAM cell are combined into a single line, and the second and third bit lines of the compensation CAM cell are combined into a single line.

7 . The leakage compensation CAM circuit of claim 5 wherein the first bit lines of the CAM cell and the compensation CAM cell are combined into a single line, the second bit lines of the CAM cell and the compensation CAM cell are combined into a single line, the third bit lines of the CAM cell and the compensation CAM cell are combined into a single line, and the fourth bit lines of the CAM cell and the compensation CAM cell are combined into a single line.

8 . The leakage compensation CAM circuit of claim 5 wherein the one or more word line drivers are coupled to the first, second, third and fourth word lines to supply output to the word lines of the CAM cell and the compensation CAM cell, and wherein the first and second word lines are controlled by mutually exclusive word line signals, and the third and fourth word lines are controlled by mutually exclusive word line signals.

9 . The leakage compensation CAM circuit of claim 5 wherein the first and third word lines are combined into a single line and the second and fourth word lines are combined into a single line.

10 . The leakage compensation CAM circuit of claim 4 wherein the sources of the second, third, fifth and sixth CAM cell transistors provide outputs representing Boolean operations between a state of the word lines and a state of the CAM cell.

11 . The leakage compensation CAM circuit of claim 1 wherein the one or more bit line drivers comprise at least one main bit line driver configured to supply output to the bit lines of the CAM cell, and wherein the main bit line driver comprises:

a first transistor;

a second transistor, wherein a drain of the second transistor is coupled to a drain of the first transistor;

a third transistor, wherein the first and third transistors are the first type transistors and the second transistor is the second type transistor;

a current source coupled to a source of the second transistor and a gate of the first transistor; and

an operational amplifier (OpAmp) comprising:

a first input terminal coupled to the source of the second transistor;

a second input terminal coupled to a bit line of the CAM cell; and

an output terminal coupled to a gate of the third transistor, wherein a source of the third transistor is coupled to the bit line of the CAM cell and wherein a drain of the third transistor provides bit line output current.

12 . The leakage compensation CAM circuit of claim 11 wherein the at least one main bit line driver is further coupled to the bit lines of the compensation CAM cell and configured to supply output to the bit lines of the compensation CAM cell.

13 . The leakage compensation CAM circuit of claim 1 wherein the one or more bit line drivers comprise at least one compensation bit line driver configured to supply output to the bit lines of the compensation CAM cell, and wherein the compensation bit line driver comprises:

a first transistor;

a second transistor, wherein a drain of the second transistor is coupled to a drain of the first transistor;

a third transistor, wherein the first and third transistors are the second type transistors and the second transistor is the first type transistor;

a current source coupled to a source of the second transistor and a gate of the first transistor; and

an operational amplifier (OpAmp) comprising:

a first input terminal coupled to the source of the second transistor;

a second input terminal coupled to a bit line of the compensation CAM cell; and

an output terminal coupled to a gate of the third transistor, wherein a source of the third transistor is coupled to the bit line of the compensation CAM cell and wherein a drain of the third transistor provides bit line output current.

14 . A leakage compensation content addressable memory (CAM) circuit, comprising:

at least one CAM cell configured to store a bit value; and

at least one compensation CAM cell configured to store the bit value of the CAM cell and to cancel leakage current of the CAM cell, wherein:

the CAM cell comprises:

a first CAM cell transistor;

a second CAM cell transistor, wherein a gate of the second CAM cell transistor is coupled to a first word line, and a source of the second CAM cell transistor is coupled to a first bit line of the CAM cell;

a third CAM cell transistor, wherein a gate of the third CAM cell transistor is coupled to a second word line, and a source of the third CAM cell transistor is coupled to a second bit line of the CAM cell;

a fourth CAM cell transistor, wherein a gate of the fourth CAM cell transistor is coupled to drains of the first, second and third CAM cell transistors;

a fifth CAM cell transistor, wherein a gate of the fifth CAM cell transistor is coupled to the first word line, and a source of the fifth CAM cell transistor is coupled to a third bit line of the CAM cell; and

a sixth CAM cell transistor, wherein a gate of the sixth CAM cell transistor is coupled to the second word line and a source of the sixth CAM cell transistor is coupled to a fourth bit line of the CAM cell, and wherein a gate of the first CAM cell transistor is coupled to drains of the fourth, fifth and sixth CAM cell transistors, wherein the first and fourth CAM cell transistors are first type transistors and the second, third, fifth and sixth CAM cell transistors are second type transistors; and

the compensation CAM cell comprises:

a first compensation CAM cell transistor;

a second compensation CAM cell transistor, wherein a gate of the second compensation CAM cell transistor is coupled to a third word line, and a source of the second compensation CAM cell transistor is coupled to a first bit line of the compensation CAM cell;

a third compensation CAM cell transistor, wherein a gate of the third compensation CAM cell transistor is coupled to a fourth word line, and a source of the third compensation CAM cell transistor is coupled to a second bit line of the compensation CAM cell,

a fourth compensation CAM cell transistor, wherein a gate of the fourth compensation CAM cell transistor is coupled to drains of the first, second and third compensation CAM cell transistors;

a fifth compensation CAM cell transistor, wherein a gate of the fifth compensation CAM cell transistor is coupled to the third word line, and a source of the fifth compensation CAM cell transistor is coupled to a third bit line of the compensation CAM cell; and

a sixth compensation CAM cell transistor, wherein a gate of the sixth compensation CAM cell transistor is coupled to the fourth word line and a source of the sixth compensation CAM cell transistor is coupled to a fourth bit line of the compensation CAM cell, and wherein a gate of the first compensation CAM cell transistor is coupled to drains of the fourth, fifth and sixth compensation CAM cell transistors, wherein the first and fourth compensation CAM cell transistors are the second type transistors and the second, third, fifth and sixth compensation CAM cell transistors are the first type transistors.

15 . The leakage compensation CAM circuit of claim 14 wherein the first type transistor is a p-channel field effect transistor (PFET) and the second type transistor is an n-channel field effect transistor (NFET), or wherein the first type transistor is the NFET and the second type transistor is the PFET.

16 . The leakage compensation CAM circuit of claim 14 further comprising:

at least one main bit line driver coupled to one or more of the first, second, third and fourth bit lines of the CAM cell to supply output to the bit lines of the CAM cell; and

at least one compensation bit line driver coupled to one or more of the first, second, third and fourth bit lines of the compensation CAM cell to supply output to the bit lines of the compensation CAM cell.

17 . The leakage compensation CAM circuit of claim 16 wherein the main bit line driver comprises:

a first transistor;

a second transistor, wherein a drain of the second transistor is coupled to a drain of the first transistor;

a third transistor, wherein the first and third transistors are the first type transistors and the second transistor is the second type transistor;

a current source coupled to a source of the second transistor and a gate of the first transistor; and

an operational amplifier (OpAmp) comprising:

a first input terminal coupled to the source of the second transistor;

a second input terminal coupled to a bit line of the CAM cell; and

an output terminal coupled to a gate of the third transistor, wherein a source of the third transistor is coupled to the bit line of the CAM cell and wherein a drain of the third transistor provides bit line output current.

18 . The leakage compensation CAM circuit of claim 16 wherein the compensation bit line driver comprises:

a first transistor;

a second transistor, wherein a drain of the second transistor is coupled to a drain of the first transistor;

a third transistor, wherein the first and third transistors are the second type transistors and the second transistor is the first type transistor;

a current source coupled to a source of the second transistor and a gate of the first transistor; and

an operational amplifier (OpAmp) comprising:

a first input terminal coupled to the source of the second transistor;

a second input terminal coupled to a bit line of the compensation CAM cell; and

an output terminal coupled to a gate of the third transistor, wherein a source of the third transistor is coupled to the bit line of the compensation CAM cell and wherein a drain of the third transistor provides bit line output current.

19 . The leakage compensation CAM circuit of claim 14 further comprising one or more word line drivers coupled to the first, second, third and fourth word lines and configured to supply outputs to the word lines of the CAM cell and the compensation CAM cell, wherein the first and second word lines are controlled by mutually exclusive word line signals, and the third and fourth word lines are controlled by mutually exclusive word line signals.

20 . The leakage compensation CAM circuit of claim 14 wherein the sources of the second, third, fifth and sixth CAM cell transistors provide outputs representing Boolean operations between a state of the word lines and a state of the CAM cell.