On-chip electrical coil and three-dimensional on-chip magnetic sensor including on-chip electrical coil
An on-chip electrical coil includes a semiconductor substrate; a plurality of metal layers disposed on the semiconductor substrate; a plurality of insulator layers disposed on the semiconductor substrate, each insulator layer disposed between a pair of neighboring metal layers to form an alternating arrangement of metal layers and insulator layers; a plurality of metal vias defined in the insulator layers, each metal via electrically connecting a respective pair of neighboring metal layers; and a planar spiral formed by the metal layers and the metal vias, the planar spiral including a plurality of interconnected loops, each loop including two metal wires disposed in respective metal layers, an intra-loop column that electrically connects the two metal wires of a respective loop, and an inter-loop column that electrically connects one of the metal wires of the respective loop to one of the metal wires in a subsequent loop.
1 . An on-chip electrical coil comprising:
a semiconductor substrate;
a plurality of metal layers disposed on the semiconductor substrate;
a plurality of insulator layers disposed on the semiconductor substrate, each insulator layer disposed between a pair of neighboring metal layers to form an alternating arrangement of metal layers and insulator layers;
a plurality of metal vias defined in the insulator layers, each metal via electrically connecting a respective pair of neighboring metal layers; and
a planar spiral formed by the metal layers and the metal vias, the planar spiral including a plurality of interconnected loops, each interconnected loop including two metal wires disposed in respective metal layers, an intra-loop column that electrically connects the two metal wires of a respective interconnected loop, and an inter-loop column that electrically connects one of the metal wires of the respective interconnected loop to one of the metal wires in a subsequent interconnected loop,
wherein:
the plurality of interconnected loops includes first and second interconnected loops,
the two metal wires of the second interconnected loop are located between the two metal wires of the first interconnected loop,
the two metal wires of the first interconnected loop include an upper metal wire disposed in an upper metal layer and a lower metal wire disposed in a lower metal layer,
the two metal wires of the second interconnected loop include a third metal wire disposed in a third metal layer and a fourth metal wire disposed in a fourth metal layer, the third and fourth metal layers between the upper and lower metal layers,
the first interconnected loop includes a first intra-loop column that electrically connects the upper and lower wires, the first intra-loop column including at least:
a first metal segment of the third metal layer,
a first metal segment of the fourth metal layer,
a first metal via that electrically connects the upper metal wire to the first metal segment of the third metal layer,
a second metal via that electrically connects the first metal segment of the third metal layer to the first metal segment of the fourth metal layer, and
a third metal via that electrically connects the first metal segment of the fourth metal layer to the lower metal wire, and
the first interconnected loop includes a first inter-loop column that electrically connects the upper metal wire to the fourth metal wire, the first inter-loop column including at least:
a second metal segment of the third metal layer,
a third metal via that electrically connects the upper metal wire to the second metal segment of the third metal layer, and
a fourth metal via that electrically connects the second metal segment of the third metal layer to the fourth metal wire.
2 . The on-chip electrical coil of claim 1 , wherein:
the two metal wires of each interconnected loop have respective lengths measured with respect to a first axis, respective widths measured with respect to a second axis that is orthogonal to the first axis, and respective heights measured with respect to a third axis that is orthogonal to the first and second axes,
the two metal wires of each interconnected loop are spatially offset from each other with respect to the third axis, and
the respective length is greater than the respective width of each metal wire.
3 . The on-chip electrical coil of claim 2 , wherein a ratio of the length to the width of each metal wire is about 500:1 to about 10,000:1.
4 . The on-chip electrical coil of claim 2 , wherein each interconnected loop extends parallel to a plane defined by the first and third axes.
5 . The on-chip electrical coil of claim 1 , wherein:
the planar spiral is a first planar spiral, and
the on-chip electrical coil further includes a second planar spiral that is electrically connected to the first planar spiral, wherein:
the interconnected loops of a respective planar spiral are wound about an axis, and
the first and second planar spirals are spatially offset from each other along the axis.
6 . The on-chip electrical coil of claim 5 , the on-chip electrical coil further includes a plurality of planar spirals, wherein:
the interconnected loops of each planar spiral are wound about the axis,
the plurality of planar spirals are spatially offset from each other along the axis, and
neighboring planar spirals are electrically connected to each other.
7 . The on-chip electrical coil of claim 6 , further comprising a plurality of intra-spiral connection wires, each intra-spiral connection wire electrically connecting first and second terminals of the neighboring planar spirals, respectively.
8 . The on-chip electrical coil of claim 6 , wherein:
the axis is a first axis,
a length of the on-chip electrical coil is measured with respect to the first axis,
a height of each planar spiral is measured with respect to a second axis,
each planar spiral is parallel to a plane defined by the first and second axes, and
the length of the on-chip electrical coil is greater than the height of each planar spiral.
9 . The on-chip electrical coil of claim 8 , wherein a ratio of the length of the on-chip electrical coil to the height of each planar spiral is about 50:1 to about 250:1.