IP Library Granted Patent US 12,299,521
Granted Patent B1
US 12,299,521 · App. 18/431,029 · Granted May 13, 2025

RFID integrated circuit identifier self-check

Inventor: Christopher J. Diorio (Shoreline, WA)
Assignee: Impinj, Inc.
G06K7/10019G06F11/1004G06F21/35G06K7/10465G06K19/0722G06K19/0723G06K19/07309
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Quick Facts
Patent No.
US 12,299,521
App. No.
18/431,029
Granted
May 13, 2025
Kind
B1
Abstract

A Radio Frequency Identification (RFID) tag IC stores an identifier and a check code. The IC determines whether the stored identifier is corrupted by comparing it to the check code. If the stored identifier does not correspond to the check code then the IC may terminate operation or indicate an error. The IC may also reconstruct the correct identifier from the check code.

Claims (66)

1. A Radio Frequency Identification (RFID) integrated circuit (IC) comprising:

a memory storing a first identifier and a check code, wherein the check code is based on and used to check a correctness of the first identifier; and

a processing block coupled to the memory and configured to:

retrieve the first identifier and the check code from the memory;

determine that the retrieved check code does not correspond to the first identifier and that the first identifier is therefore corrupted by at least one of:

comparing the retrieved check code to the first identifier; and

computing a check code from the first identifier and comparing the retrieved check code with the computed check code; and

in response to the determination, terminate operation of the RFID IC.

2. The RFID IC of claim 1 , wherein the processing block is configured to retrieve the first identifier and the check code from the memory upon the RFID IC extracting an operating power from an RF signal.

3. The RFID IC of claim 1 , wherein the processing block is configured to terminate the operation of the RFID IC by causing the RFID IC to at least one of:

power down;

kill the RFID IC; or

refrain from responding to external commands.

4. The RFID IC of claim 1 , wherein the first identifier includes a code indicating at least one of an attribute of the RFID IC and an attribute of an item associated with the RFID IC.

5. The RFID IC of claim 1 , wherein at least one bit of the retrieved check code is stored in a complementary half of a differential memory cell.

6. The RFID IC of claim 1 , wherein the retrieved check code includes at least one of:

at least one memory-redundancy bit,

at least one parity bit,

a checksum,

a cyclic redundancy check,

a hash function output, or

an error-correcting code.

7. A Radio Frequency Identification (RFID) integrated circuit (IC) comprising:

a memory storing a first code and a check code, wherein the check code is based on and used to check a correctness of the first code; and

a processing block coupled to the memory and configured to:

retrieve the first code and the check code from the memory;

determine that the retrieved check code does not correspond to the first code and that the first code is therefore corrupted by at least one of:

comparing the retrieved check code to the first code; and

computing a check code from the first code and comparing the retrieved check code with the computed check code; and

in response to the determination, terminate operation of the RFID IC.

8. The RFID IC of claim 7 , wherein the processing block is configured to retrieve the first code and the check code from the memory upon the RFID IC extracting an operating power from an RF signal.

9. The RFID IC of claim 7 , wherein the processing block is configured to terminate operation of the RFID IC by causing the RFID IC to at least one of:

power down;

kill the RFID IC; or

refrain from responding to external commands.

10. The RFID IC of claim 7 , wherein the first code indicates at least one of an attribute of the RFID IC and an attribute of an item associated with the RFID IC.

11. The RFID IC of claim 7 , wherein the first code is an identifier for at least one of the RFID IC and an item associated with the RFID IC.

12. The RFID IC of claim 7 , wherein at least one bit of the retrieved check code is stored in a complementary half of a differential memory cell.

13. The RFID IC of claim 7 , wherein the retrieved check code includes at least one of:

at least one memory-redundancy bit,

at least one parity bit,

a checksum,

a cyclic redundancy check,

a hash function output, or

an error-correcting code.

14. A method for a Radio Frequency Identification (RFID) integrated circuit (IC), the method comprising:

retrieving, from an IC memory, a first code and a check code, wherein the check code is based on and used to check a correctness of the first code;

determining that the retrieved check code does not correspond to the first code and that at least one of the check code and the first code is therefore corrupted by at least one of:

comparing the retrieved check code to the first code; and

computing a check code from the first code and comparing the retrieved check code with the computed check code; and

in response to the determination, terminating operation of the RFID IC.

15. The method of claim 14 , further comprising retrieving the first code and the check code from the memory upon the RFID IC extracting an operating power from an RF signal.

16. The method of claim 14 , further comprising terminating operation of the RFID IC by at least one of:

powering down;

killing the RFID IC; or

refraining from responding to external commands.

17. The method of claim 14 , wherein the first code indicates at least one of an attribute of the RFID IC and an attribute of an item associated with the RFID IC.

18. The method of claim 14 , wherein the first code is an identifier for at least one of the RFID IC and an item associated with the RFID IC.

19. The method of claim 14 , wherein at least one bit of the retrieved check code is stored in a complementary half of a differential memory cell.

20. The method of claim 14 , wherein the retrieved check code includes at least one of:

at least one memory-redundancy bit,

at least one parity bit,

a checksum,

a cyclic redundancy check,

a hash function output, or

an error-correcting code.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2024
From: DIORIO, CHRISTOPHER J.
To: IMPINJ, INC.
Reel/Frame 066347/0695 →
Continuity (7)
Continuation 17749585 · May 20, 2022
Continuation 17019385 · Sep 14, 2020
Continuation 16569680 · Sep 13, 2019
Continuation 15251152 · Aug 30, 2016
Continuation 14959153 · Dec 4, 2015
Continuation 13865993 · Apr 18, 2013
Provisional Application 61723944 · Nov 8, 2012
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