Tri-layer semiconductor stacks for patterning features on solar cells
Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.
1 . A solar cell, comprising:
a first thin dielectric layer on a back surface of a substrate;
a semiconductor structure on the first thin dielectric layer such that the first thin dielectric layer is vertically between the back surface of the substrate and the semiconductor structure, wherein the semiconductor structure comprises a stack of three or more distinct semiconductor layers, the three or more distinct semiconductor layers comprising a first semiconductor layer comprising an outermost edge, a second semiconductor layer on the first semiconductor layer, the second semiconductor layer comprising a sloped outermost edge, and a third semiconductor layer on the second semiconductor layer, the third semiconductor layer comprising a third outermost edge, wherein the third outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer, and wherein the semiconductor structure has an uppermost surface;
a second thin dielectric layer on the back surface of the substrate;
a polycrystalline silicon emitter region on the second thin dielectric layer, wherein the polycrystalline silicon emitter region has an uppermost surface at a same level as the uppermost surface of the semiconductor structure;
a first conductive contact structure on the semiconductor structure; and
a second conductive contact structure on the polycrystalline silicon emitter region.
2 . The solar cell of claim 1 , wherein the stack of the semiconductor structure is a tri-layer semiconductor stack.
3 . The solar cell of claim 1 , wherein the stack of the semiconductor structure comprises:
first semiconductor layer on the first thin dielectric layer;
wherein the second semiconductor layer is a P-type semiconductor layer on the first semiconductor layer; and
the third semiconductor layer on the P-type semiconductor layer.
4 . The solar cell of claim 1 , wherein the first and second thin dielectric layer comprise silicon dioxide.
5 . The solar cell of claim 1 , wherein a portion of the back surface comprises a texturized surface.
6 . The solar cell of claim 1 , wherein the polycrystalline silicon emitter region is N-type.
7 . The solar cell of claim 1 , wherein the first and second conductive contact structures each comprises an aluminum-based metal seed layer on the semiconductor structure and the polycrystalline silicon emitter region, respectively, and each further comprises a metal layer on the aluminum-based metal seed layer.
8 . The solar cell of claim 1 , further comprising:
a third thin dielectric layer on a light-receiving surface of the substrate;
a polycrystalline silicon layer on the third thin dielectric layer; and
an anti-reflective coating (ARC) layer on the polycrystalline silicon layer.
9 . A solar cell, comprising:
a first dielectric layer on a back surface of a substrate;
a semiconductor stack on the first dielectric layer such that the first dielectric layer is vertically between the back surface of the substrate and the semiconductor stack, wherein the semiconductor stack comprises a stack of three or more distinct semiconductor layers, the three or more distinct semiconductor layers comprising a first semiconductor layer comprising an outermost edge, a second semiconductor layer on the first semiconductor layer, the second semiconductor layer comprising a sloped outermost edge, and a third semiconductor layer on the second semiconductor layer, the third semiconductor layer comprising a third outermost edge, wherein the third outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer, and wherein the semiconductor stack has an uppermost surface;
a second dielectric layer on the back surface of the substrate;
a polycrystalline silicon emitter region on the second dielectric layer, wherein the polycrystalline silicon emitter region has an uppermost surface at a same level as the uppermost surface of the semiconductor stack;
a first conductive contact structure on the semiconductor stack; and
a second conductive contact structure on the polycrystalline silicon emitter region.
10 . The solar cell of claim 9 , wherein the stack of the semiconductor stack is a tri-layer semiconductor stack.
11 . The solar cell of claim 9 , wherein the stack of the semiconductor stack comprises:
the first semiconductor layer on the first dielectric layer;
wherein the second semiconductor layer is a P-type semiconductor layer on the first semiconductor layer; and
the third semiconductor layer on the P-type semiconductor layer.
12 . The solar cell of claim 9 , wherein the first and second dielectric layer comprise silicon dioxide.
13 . The solar cell of claim 9 , wherein the polycrystalline silicon emitter region is N-type.
14 . The solar cell of claim 9 , wherein the first and second conductive contact structures each comprises an aluminum-based metal seed layer on the semiconductor stack and the polycrystalline silicon emitter region, respectively, and each further comprises a metal layer on the aluminum-based metal seed layer.
15 . The solar cell of claim 9 , further comprising:
a third dielectric layer on a light-receiving surface of the substrate;
a polycrystalline silicon layer on the third dielectric layer; and
an anti-reflective coating (ARC) layer on the polycrystalline silicon layer.
16 . A solar cell, comprising:
a first thin dielectric layer on a back surface of a substrate;
a first semiconductor layer on the first thin dielectric layer, the first semiconductor layer comprising an outermost edge;
a second semiconductor layer on the first semiconductor layer, the second semiconductor layer comprising a sloped outermost edge; and
a third semiconductor layer on the second semiconductor layer, the third semiconductor layer comprising a third outermost edge, wherein the third outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer, wherein the third semiconductor layer has an uppermost surface;
a second thin dielectric layer on the back surface of the substrate;
a polycrystalline silicon emitter region on the second thin dielectric layer, wherein the polycrystalline silicon emitter region has an uppermost surface at a same level as the uppermost surface of the third semiconductor layer;
a first conductive contact structure on the third semiconductor layer; and
a second conductive contact structure on the polycrystalline silicon emitter region.
17 . The solar cell of claim 16 , wherein the second semiconductor layer comprises a P-type semiconductor layer.
18 . The solar cell of claim 16 , wherein the polycrystalline silicon emitter region is N-type.
19 . The solar cell of claim 16 , wherein the first and second conductive contact structures each comprises an aluminum-based metal seed layer on the third semiconductor layer and polycrystalline silicon emitter region, respectively, and each further comprises a metal layer on the aluminum-based metal seed layer.
20 . The solar cell of claim 16 , further comprising:
a third thin dielectric layer on a light-receiving surface of the substrate;
a polycrystalline silicon layer on the third thin dielectric layer; and
an anti-reflective coating (ARC) layer on the polycrystalline silicon layer.