PLL circuit and transmission system
A phase-locked loop (PLL) circuit generates an output clock signal and includes: a selection circuit that selects one of a plurality of clock signals as a reference clock signal of the PLL circuit; and a control circuit that when a switch is made for the selection of the reference clock signal, temporarily reduces a division ratio used by a frequency divider that generates a feedback clock signal to be compared with the reference clock signal.
1. A phase-locked loop (PLL) circuit that generates an output clock signal, the PLL circuit comprising:
a selection circuit that selects one of a plurality of clock signals as a reference clock signal of the PLL circuit; and
a control circuit that when a switch is made for the selection of the reference clock signal, temporarily reduces a division ratio used by a frequency divider that generates a feedback clock signal to be compared with the reference clock signal,
wherein the control circuit resets the frequency divider when the switch is made for the selection of the reference clock signal, and
a period in which the division ratio is temporarily reduced is a single cycle or a plurality of cycles of the feedback clock signal immediately after reset cancel of the frequency divider.
2. The PLL circuit according to claim 1 , wherein
when the switch is made for the selection of the reference clock signal, the control circuit temporarily masks a detection result obtained by a phase comparator in the PLL circuit.
3. The PLL circuit according to claim 2 , wherein
the control circuit cancels the masking when a phase difference between the reference clock signal and the feedback clock signal is less than a threshold.
4. The PLL circuit according to claim 1 , further comprising:
an oscillator that generates the output clock signal;
a phase comparator that detects a phase difference between the reference clock signal and a feedback clock signal output from the frequency divider; and
a filter circuit that outputs, to the oscillator, a control signal in accordance with the phase difference detected.
5. The PLL circuit according to claim 4 , wherein
when the switch is made for the selection of the reference clock signal, the control circuit temporarily masks a signal indicating the phase difference generated by the phase comparator.
6. A phase-locked loop (PLL) circuit that generates an output clock signal, the PLL circuit comprising:
a selection circuit that selects one of a plurality of clock signals as a reference clock signal of the PLL circuit; and
a control circuit that when a switch is made for the selection of the reference clock signal, temporarily reduces a division ratio used by a frequency divider that generates a feedback clock signal to be compared with the reference clock signal, wherein
the control circuit temporarily changes the division ratio from N to (N-m) when the switch is made for the selection of the reference clock signal, where N is an integer indicating a division ratio in a locked state before the reference clock signal is switched, and m is an integer corresponding to a time difference between an edge timing of the reference clock signal immediately after the reference clock signal is switched and a start timing of the frequency divider immediately after reset cancel.
7. The PLL circuit according to claim 1 , wherein
the control circuit outputs a division ratio switching signal to the frequency divider, and
the frequency divider starts dividing a frequency at a small division ratio in a period in which the division ratio switching signal is being asserted.
8. A phase-locked loop (PLL) circuit that generates an output clock signal, the PLL circuit comprising:
a selection circuit that selects one of a plurality of clock signals as a reference clock signal of the PLL circuit; and
a control circuit that when a switch is made for the selection of the reference clock signal, temporarily reduces a division ratio used by a frequency divider that generates a feedback clock signal to be compared with the reference clock signal, wherein
the selection circuit has a stop period during which the selection circuit does not output the reference clock signal when the switch is made for the selection of the reference clock signal, and
the control circuit brings the frequency divider into a reset state in the stop period and cancels the reset state of the frequency divider at an edge timing of the reference clock signal, the edge timing occurring when the stop period is ended.
9. The PLL circuit according to claim 1 , wherein
the selection circuit does not output glitch noise when the switch is made for the selection of the reference clock signal.
10. A transmission system comprising:
the PLL circuit according to claim 1 ;
a converter that converts parallel data into serial data in synchronization with the output clock signal; and
a transmission driver that outputs the serial data to a communication line.