Memory device memory including an antifuse cell array
The present disclosure relates to memory devices. An example memory device includes a memory cell region including a memory cell array is configured to store data, and an antifuse cell array including a plurality of antifuse bit lines, a plurality of antifuse word lines, and a plurality of program transistors that is electrically coupled to a first antifuse bit line among the plurality of antifuse bit lines and that are coupled in parallel with one another. The memory device includes a peripheral circuit region including an antifuse sense amplifier is configured to output one-time programmable (OTP) data stored in the plurality of program transistors.
1 . A memory device comprising:
a memory cell region, the memory cell region including:
a memory cell array that is configured to store data, and
an antifuse cell array that includes an antifuse cell; and
a peripheral circuit region, wherein at least a portion of the peripheral circuit region overlaps the memory cell region in a plan view, the peripheral circuit region is stacked with the memory cell region in a vertical direction, and the peripheral circuit region includes an antifuse sense amplifier that is configured to output one-time programmable (OTP) data stored in the antifuse cell.
2 . The memory device of claim 1 , wherein
the OTP data stored in the antifuse cell corresponds to one bit, and
the antifuse cell includes at least three transistors.
3 . The memory device of claim 2 , wherein
the antifuse cell array includes a plurality of program word lines, and
the antifuse cell includes at least two program transistors that are operated by a program word line of the plurality of program word lines.
4 . The memory device of claim 2 , wherein
the antifuse cell array includes a plurality of antifuse bit lines, the plurality of antifuse bit lines including a first antifuse bit line, a second antifuse bit line, and a third antifuse bit line,
the antifuse sense amplifier includes a first antifuse sense amplifier that is configured to output first output data based on a signal input from the first antifuse bit line, a second antifuse sense amplifier that is configured to output second output data based on a signal input from the second antifuse bit line, and a third antifuse sense amplifier that is configured to output third output data based on a signal input from the third antifuse bit line, and
the peripheral circuit region includes a majority voting circuit that is configured to receive the first output data, the second output data, and the third output data.
5 . The memory device of claim 4 , wherein
the majority voting circuit is configured to output, as the OTP data, data corresponding to a majority of the first output data, the second output data, and the third output data.
6 . The memory device of claim 1 , wherein
the antifuse sense amplifier overlaps at least a portion of the antifuse cell array in a planar manner.
7 . The memory device of claim 1 , wherein
the peripheral circuit region includes a substrate, and
the antifuse cell includes a vertical-channel layer that extends in a vertical direction of the substrate.
8 . The memory device of claim 7 , wherein
the vertical-channel layer contains at least one of silicon or Indium Gallium Zinc Oxide (IGZO).