Read synchronization delay at subordinate device for 1 wire protocol
A subordinate device includes a local clock and a protocol controller. The protocol controller is coupled to a bus that includes a data wire. The protocol controller is configured to receive, on the data wire from a principal device, a read command addressed to the subordinate device indicating initiation of a read transaction. The protocol controller is also configured to, after a delay window, send synchronization pulses to the principal device based on the local clock, where a duration of the delay window is greater than a clock cycle of the local clock. The protocol controller is further configured to, after sending the synchronization pulses, send data on the data wire to the principal device based on the local clock during the read transaction.
1. A subordinate device comprising:
a local clock; and
a protocol controller coupled to a bus that includes a data wire, the protocol controller configured to:
receive, on the data wire from a principal device, a read command addressed to the subordinate device indicating initiation of a read transaction;
after a delay window, send synchronization pulses to the principal device based on the local clock, wherein a duration of the delay window is greater than a clock cycle of the local clock; and
after sending the synchronization pulses, send data on the data wire to the principal device based on the local clock during the read transaction.
2. The subordinate device of claim 1 , wherein the duration of the delay window is based on memory access latency, a configuration of the bus, or both.
3. The subordinate device of claim 1 , wherein the protocol controller is configured to, responsive to receiving the read command:
initialize a counter based on the duration of the delay window;
update the counter at each clock cycle of the local clock; and
send the synchronization pulses in response to the counter reaching a particular value.
4. The subordinate device of claim 1 , wherein the duration of the delay window is pre-determined.
5. The subordinate device of claim 1 , wherein the duration of the delay window is based on a memory access time associated with arrival of the data.
6. The subordinate device of claim 1 , wherein the protocol controller is configured to:
initiate a memory access of the data responsive to receiving the read command; and
send the synchronization pulses in response to arrival of the data.
7. The subordinate device of claim 1 , wherein the protocol controller is configured to:
responsive to receiving the read command, initialize a counter and initiate a memory access of the data; and
update the counter at each clock cycle of the local clock.
8. The subordinate device of claim 7 , wherein the protocol controller is configured to send termination pulses to the principal device in response to the counter reaching a particular value prior to arrival of the data, the termination pulses corresponding to a termination of the read transaction.
9. The subordinate device of claim 7 , wherein the protocol controller is configured to send the synchronization pulses to the principal device in response to arrival of the data prior to the counter reaching a particular value.
10. A method comprising:
receiving, at a subordinate device on a data wire of a bus from a principal device, a read command addressed to the subordinate device indicating initiation of a read transaction;
after a delay window, sending synchronization pulses from the subordinate device to the principal device based on a local clock of the subordinate device, wherein a duration of the delay window is greater than a clock cycle of the local clock; and
after sending the synchronization pulses, sending data from the subordinate device on the data wire to the principal device based on the local clock during the read transaction.
11. The method of claim 10 , wherein the duration of the delay window is based on memory access latency, a configuration of the bus, or both.
12. The method of claim 10 , further comprising, responsive to receiving the read command:
initializing a counter based on the duration of the delay window; and
updating the counter at each clock cycle of the local clock, wherein the synchronization pulses are sent in response to the counter reaching a particular value.
13. The method of claim 10 , wherein the duration of the delay window is pre-determined.
14. The method of claim 10 , wherein the duration of the delay window is based on a memory access time associated with arrival of the data.
15. The method of claim 10 , further comprising initiating a memory access of the data responsive to receiving the read command, wherein the synchronization pulses are sent in response to arrival of the data.
16. The method of claim 10 , further comprising:
responsive to receiving the read command, initializing a counter and initiating a memory access of the data; and
updating the counter at each clock cycle of the local clock.
17. The method of claim 16 , wherein the synchronization pulses are sent to the principal device in response to arrival of the data prior to the counter reaching a particular value.
18. A non-transitory computer-readable medium storing instructions that, when executed by one or more processors, cause the one or more processors to:
receive, at a subordinate device on a data wire of a bus from a principal device, a read command addressed to the subordinate device indicating initiation of a read transaction;
after a delay window, send synchronization pulses from the subordinate device to the principal device based on a local clock of the subordinate device, wherein a duration of the delay window is greater than a clock cycle of the local clock; and
after sending the synchronization pulses, send data from the subordinate device on the data wire to the principal device based on the local clock during the read transaction.
19. The non-transitory computer-readable medium of claim 18 , wherein the duration of the delay window is based on memory access latency, a configuration of the bus, or both.
20. The non-transitory computer-readable medium of claim 18 , wherein the instructions, when executed by the one or more processors, cause the one or more processors to, responsive to receiving the read command:
initialize a counter based on the duration of the delay window;
update the counter at each clock cycle of the local clock; and
send the synchronization pulses in response to the counter reaching a particular value.